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# DFT DV Engineer, AI Hardware

- **Company:** Tesla Motors
- **Location:** Palo Alto, CA, United States
- **Experience:** Experienced
- **Salary:** $128,000.0 - $312,000.0
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Software Debugging, Formal Verification, Joint Test Action (IEEE Standards), Test Case, Hardware Acceleration
- **Published:** October 11, 2026
- **Apply:** https://diversityjobs.com/career/16629165/Staff-Dft-Dv-Engineer-Ai-Hardware-California-Palo-Alto

## About the Role

* Degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience
 * 3+ years of DFT DV experience at block and SoC level
 * Expert-levelSystemVerilogand UVM testbench development
 * Hands-on verification of SSN, compressed scan, MBIST, JTAG, and boundary scan
 * Experience delivering pre-Si testcases through silicon bring-up and ATE correlation
 * Ability to use agentic AI flows to automate DV regression and debug workflows
 * Post-silicon debug and ATE correlation experience on server-class SoCs
 * Familiarity with formal verification methods for DFT structural checks
 * Experience with power-on self-test and clock control verification

## Description

Our Silicon Engineering team validates DFT features from RTL through silicon bring-up - ensuring test structures work correctly before the chip reaches the tester. As a Staff DFT DV Engineer, you will own functional verification of all DFT structures at block and SoC level, delivering pre-Si testcases that directly enable silicon debug and ATE correlation.
What You'll Do

 * DevelopSystemVerilog/UVM testbenches to verify DFT features - SSN, compressed scan, memory BIST, JTAG, and boundary scan at block and SoC level
 * Verify top-level DFT features - power-on self-test, clock observation, clock stop, and scan dump
 * Run DV regressions, analyze coverage,triageand debug failures to closure
 * Identifydesign fixes and validate DFT RTL corrections
 * Deliver pre-Si DV testcases for silicon bring-up and ATE correlation
 * Own post-silicon ATE test correlation - root cause discrepancies between pre-Si and silicon behavior
 * Leverage agentic AI flows to automate regression execution, coverage analysis, and failure triage