> Markdown version of [/jobs/ext/3689843-staff-engineer-digital-verification-and-methodology](https://www.wearedevelopers.com/jobs/ext/3689843-staff-engineer-digital-verification-and-methodology). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Staff Engineer Digital Verification and Methodology - **Company:** Infineon Technologies LLC - **Location:** United States - **Salary:** $98,560.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Firmware, Process Driven Development, Subsystems, SystemVerilog, Information Technology - **Published:** October 11, 2026 - **Apply:** https://www.dice.com/job-detail/8ee136be-2804-4f08-892b-e9171558b3ee ## About the Role * Mandatory: Bachelor's or Master's degree inElectrical Engineering, Computer Engineering, Computer Science or a relatedfield, or equivalent practical experience * Mandatory: Demonstrated experience in digital verificationand verification methodology development for complex IP, subsystems orSoCs * Mandatory: Expert knowledge of SystemVerilog and UVMwith a strong understanding of digital design, verificationarchitectures and constrained-random techniques * Mandatory: Proven ability to develop verification environmentsand reusable assets including specifications, assertions, coveragestrategies and Verification IP * Mandatory: Strong analytical and debugging skills with theability to provide technical direction and collaborate across globalcross-functional teams; English: Written and spoken * Preferred: Experience with formal and assertion-basedverification, firmware-driven verification, microcontroller-basedICs or automotive, safety or security requirements * Nice-to-have: Familiarity with regression automation and verificationinfrastructure, mentoring or methodology adoption leadership,or applying AI-based engineering approaches #LI-AOO ## Description * Defineverification concepts, strategies and measurable plans fordigital IP, subsystems and SoC projects * Develop and maintain SystemVerilog and UVM verificationenvironments, reusable components and Verification IP * Create verification specifications, test scenarios, assertions,coverage strategies and closure criteria * Apply constrained-random, metric-driven and formalverification techniques to validate complex designs * Lead methodology capabilities including roadmap definition, requirements,implementation, documentation, enablement, adoptionand continuous improvement * Evaluate and apply AI-based methodologies for verification planning,test generation, debug, coverage analysis, knowledgereuse and workflow automation * Collaborate with concept, design, application engineeringand methodology teams to communicate technical direction, status,risks and quality metrics Your profile Youare a collaborative problem solver who communicates clearly and thrives incross-functional environments. You combine a structured, analytical mindsetwith a passion for enabling others through robust methodology and automation