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# Sr. SoC Power Engineer, Annapurna Labs - Cloud Scale Machine Learning

- **Company:** Amazon.com, Inc.
- **Location:** Cupertino, CA, United States
- **Experience:** Expert
- **Salary:** $213,000.0 - $287,500.0
- **Contract:** Permanent contract
- **Skills:** Cloud Computing, Computer Engineering, Perl (Programming Language), Emulators, Python (Programming Language), Machine Learning, SystemVerilog, Tcl (Programming Language), Scripting, Information Technology, Power Analysis (Cryptography), Physical Design
- **Published:** October 11, 2026
- **Apply:** https://dejobs.org/x/x/A18BA92A74B7432B82F7F3269D745E7B/job/

## About the Role

We're searching for an experienced SoC Power engineer with a background in Power analysis with a proven track record of handling challenges at scale. In this role, you'll be working directly with architects, designers, verification engineers, software teams, and Physical Design experts - defining best practices to reduce power and model power consumption with high accuracy., * Bachelor's degree in Computer Science, Computer Engineering, or Electrical Engineering

 * BS + 6yrs or MS + 5yrs or PhD + 3yr in EE/CS
 * Expert on power analysis tools like PrimePower, PowerArtist or similar
 * Ability to give feedback to RTL designers and Physical Designers on how to reduce power
 * Highly proficient with scripting language (Tcl, Perl, Python or similar)
 * Good understanding of Physical Design, EM/IR, Power Integrity, and Thermal at the die, package, board, and server level
 * Understanding of lab equipment use and capable of doing lab power analysis
 * Knowledge of deep circuit-level chip power, * Familiarity with Make or similar for automation of power rollups
 * Experience with RTL design (System verilog)
 * Familiarity with EMIR analysis tools (Redhawk / Voltus)
 * Experience with Zebu Emulator platform

## Description

* Responsible for full chip power analysis & modelling at various stages of design (RTL to gate level netlist)
 * Develop and maintain dashboards for power rollups
 * Work with designers, architects, Verification engineers and Physical Design engineers to develop vectors for IR analysis, Thermal analysis and power estimation
 * Give feedback to designers and architects on how to reduce power
 * Make power measurements in the lab and correlate back to simulations.
 * Work with Emulation engineers to model chip-level power consumption

A day in the life

Depending on the state of the project, you may find yourself working on the following:

 * Working with designers, architects and verification engineers to come up with worst-case vectors for power analysis or IR analysis
 * Root cause causes of low annotation or low switching coverage with vectors
 * Develop & maintain dashboards to track power consumption
 * Run tools like Power Artist to identify power saving opportunities and feed these back to the design team.
 * Work with emulation engineers to model chip level power consumption and correlate with simulation
 * Do post-silicon power measurements and correlate with simulation.