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# RTL integration Engineer

- **Company:** LINKED, LLC
- **Location:** San Jose, CA, United States
- **Salary:** $143,800.0 - $230,000.0
- **Contract:** Permanent contract
- **Skills:** Software Debugging, SystemVerilog
- **Published:** October 12, 2026
- **Apply:** https://www.juju.com/job/1_broadcomwd-R026729

## About the Role

Strong debugging skills are highly required. **Requirements:** + Extensive knowledge of implementation, synthesis, and timing issues. + Strong understanding of UVM and SystemVerilog is required. + Deep familiarity with zero-delay and SDF simulations, including the ability to debug failures effectively. + Proven experience in gate-level simulation (GLS). + Familiarity with Clock Domain Crossing (CDC) analysis for both RTL and gate-level designs. + Highly desirable experience with simulation tools such as NCSim and VCS. + Ability to work independently with minimal supervision. + Experience working within a global team and a dynamic environment. + Strong ability to quickly learn and adapt to new tools and methodologies. + Excellent communication skills are a must. **Education and Experience:** + Bachelors and 12+ years of related experience; **Compensation and Benefits** The annual base salary range for this position is USD 143,800.00 To USD 230,000.00 As a valued member of our