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# SoC Performance Analysis Engineer

- **Company:** Apple Inc.
- **Location:** Santa Clara, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Software Debugging, Perl (Programming Language), Python (Programming Language), SystemVerilog, Verilog, Scripting, Hardware Infrastructure
- **Published:** October 12, 2026
- **Apply:** https://www.juju.com/job/1_apple2-200664333

## About the Role

Have strong interpersonal skills, work independently & lead work you're doing to align with the project goals plus support multi-functional engineering efforts. **Minimum Qualifications** + Bachelors degree + 10 years of industry experience **Preferred Qualifications** + You are well-rounded in performance correlation and analysis and are an extraordinary teammate with excellent social skills. + You have the desire to solve diverse challenges. + Sophisticated knowledge of CPU & SOC architecture/design + Familiarity with verification environments and Verilog, C/C++. + Experience with SystemVerilog, Verilog and scripting in Perl/Python Apple is an equal opportunity employer that is committed to inclusion and diversity.
We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.

## Description

Imagine what you could do here!
At Apple, our new insights have a way of becoming extraordinary products, services, and customer experiences very quickly.
We bring passion and dedication to our job and when you are a part of our team there's no telling what you could accomplish.
The SoC Performance Verification is a critical job within Apple's Hardware Technology.
Joining this group means you will be responsible for crafting and building the technology that fuels Apple's devices.
Together, you and your team will enable our customers to do all the things they love with their devices. **Description** Work closely with Architecture to understand performance goals of the design.
Correlate RTL performance against model performance.
Perform deep performance analysis in the design and report findings.
Identify performance bottlenecks and coordinate with Design and Architecture teams to improve performance.
Define performance statistics to help performance debug and standard methodologies to improve performance correlation effort.