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# Full Chip Timing Modeling and Integration Engineer

- **Company:** Altera Corporation
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $133,200.0 - $192,825.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Computer Engineering, Software Debugging, Electronic Design Automation, Field-Programmable Gate Array (FPGA), Python (Programming Language), Machine Learning, PCI Express, Static Timing Analysis, Tcl (Programming Language), Verilog, Backend, Information Technology, Front End Software Development
- **Published:** October 12, 2026
- **Apply:** https://www.dice.com/job-detail/85496c98-f104-47df-a402-3172d4e32586

## About the Role

* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 5+ years of industry experience in SoC development.
 * 5+ years of industry experience working with advanced semiconductor process nodes.
 * 5+ years of industry experience with industry-standard timing formats and design constraints, including Liberty, Verilog, and Synopsys Design Constraints (SDC).
 * 5+ years of industry experience with Static Timing Analysis (STA), including correlating STA results with SPICE.
 * 5+ years of industry experience in timing modeling and library quality assurance (QA).
 * 5+ years of industry experience writing Python and Tcl scripts for design automation.
 * 5+ years of industry experience applying silicon modeling concepts, such as LVF and POCV.

Preferred Qualifications

 * 7+ years of relevant industry experience.
 * Experience completing several complex designs involving multiple voltage domains.
 * Experience with common modes of operation, including functional and Design-for-Test (DFT), for use in timing constraint review and management.
 * Experience in the architecture and/or design of FPGA, DDR, PCIe, or related technologies.
 * Experience actively applying AI/ML techniques to improve and optimize execution.

## Description

Altera is seeking highly qualified candidates to join our Full Chip Timing team. Altera continues to deliver industry-leading Field-Programmable Gate Array (FPGA) solutions to customers.

As a Full Chip Timing Modeling and Integration Engineer, you will develop timing methodologies and execute full-chip timing for Altera's next-generation product lines using the world's most advanced process technologies.

This is a fast-paced, dynamic environment where you will be part of a high-performance design team working toward next-generation FPGA products. You will work hands-on performing full-chip timing analysis, leveraging your extensive design experience and interpersonal skills to solve technical issues, drive continuous improvement, and clearly communicate technical trade-offs with diverse, cross-functional, and multi-site teams.

You will collaborate with cross-functional teams to define timing modeling strategies and solutions, generate high-level timing models, and integrate and validate timing models. Success in this role requires the ability to work effectively both independently and as part of a team while meeting aggressive schedules.

Responsibilities

 * Develop timing methodologies and execute full-chip timing for next-generation FPGA products using advanced process technologies.
 * Collaborate with cross-functional teams to define timing modeling strategies and solutions.
 * Generate high-level timing models and perform timing model integration and validation.
 * Perform hands-on full-chip timing analysis, including clocking and timing constraint development.
 * Work with Front-End and Back-End design teams to understand design architecture and implementation.
 * Analyze extraction issues, design margins, timing signoff requirements, and timing quality checks.
 * Debug and troubleshoot a wide variety of technical issues, including difficult and critical design issues, and proactively intervene to resolve them.
 * Drive continuous improvement, efficiently solve technical issues, and communicate technical trade-offs across cross-functional and multi-site teams.
 * Work independently and collaboratively to deliver high-quality results within aggressive project schedules.