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# Senior ASIC DFT DV Engineer (Hybrid)

- **Company:** Cisco Systems, Inc.
- **Location:** New York, NY, United States
- **Experience:** Expert
- **Salary:** $167,700.0 - $245,200.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Software Debugging, Perl (Programming Language), Joint Test Action (IEEE Standards), Python (Programming Language), Routing, System Testing, SystemVerilog, Tcl (Programming Language), Strategies of Testing, Application Specific Integrated Circuits, Cisco
- **Published:** October 15, 2026
- **Apply:** https://diversityjobs.com/career/18634571/Senior-Asic-Dft-Dv-Engineer-Hybrid-California-San-Jose

## About the Role

* Bachelor's in Electrical Engineering or equivalent with at least 7+ years (or Master's with 4+ years) of experience.
 * Prior experience in test planning based on complex design specifications.
 * Prior experience in testbench development using System Verilog.
 * Experience debugging using DVE/Verdi.
 * Experience with TCL, Python or Perl.

Preferred Qualifications

 * UVM and advanced System Verilog knowledge.
 * Knowledge about JTAG protocol, scan architecture, MBIST and boundary scan.

## Description

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development-from design to qualification to production-is within our team, we're able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Your Impact

 * Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design
 * Collaborate with the design/design-verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation and post silicon validation flows.
 * Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug methodologies and standards.
 * The job requires the candidate to have the ability to craft solutions anddebug efficiently.