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# Staff Clock & Reset Architecture Engineer, SI Hardware

- **Company:** Tesla Motors
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Multiplexing, Perl (Programming Language), Python (Programming Language), Software Requirements Analysis, System on a Chip, SystemVerilog, Tcl (Programming Language), Verilog, Scripting, Application Specific Integrated Circuits, Information Technology, Physical Design
- **Published:** October 15, 2026
- **Apply:** https://jobs.localjobnetwork.com/apply/add/87747159/1

## About the Role

* 8+ years ASIC/SoC design experience
 * Deep expertise in clock architecture, distribution, muxing, dividers, and PLL integration
 * Proven skill in reset architecture, sequencing, and domain-crossing solutions
 * Strong knowledge of CDC and RDC methodologies
 * Proficient in STA constraints, timing closure for multi-clock designs, and clock-tree synthesis
 * Extensive RTL development using Verilog/SystemVerilog and scripting (Python/Tcl/Perl)
 * Worked on large multi-billion-gate SoCs with DFT considerations for clock and reset
 * Familiar with industry tools: CDC/RDC analysis tools, PrimeTime/Tempus
 * Degree in Electrical Engineering, Computer Science, or equivalent field or equivalent experience

## Description

We are seeking a Staff Clock & Reset Architecture Engineer to lead the clock and reset architecture for next generation SoCs. In this high visibility position you will define scalable multi-clock systems, integrate PLL-based clock generation, and ensure reliable operation across multiple clock and reset domains. You'll collaborate closely with architecture, RTL, verification, timing, and physical design teams to deliver robust clocking and reset infrastructure that drives performance, silicon reliability, and correctness for complex multi-domain chips.
What You'll Do

 * Deliver functional IP blocks into the target SoC, ensuring they meet all architectural and software requirements
 * Evaluate existing internal and external IP to understand functionality, interfaces, and integration constraints
 * Analyze and optimize timing, performance, and area (PPA) across the design
 * Diagnose and resolve clock-tree and reset-distribution issues to guarantee robust system operation
 * Specify, micro-architect, and RTL-code clock generation, distribution, and reset sequencing logic
 * Balance trade-offs among functional, physical, and performance targets, making data-driven decisions
 * Partner with cross-functional teams (implementation, verification, performance engineering) throughout the design flow
 * Design for synthesis readiness, adhering to best-practice coding styles and tool constraints