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# ASIC RTL Design Engineer, SI Hardware

- **Company:** Tesla Motors
- **Location:** Palo Alto, CA, United States
- **Experience:** Expert
- **Salary:** $160,000.0 - $312,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Microarchitecture, Software Debugging, Logic Synthesis of Circuits, System on a Chip, Verilog, Application Specific Integrated Circuits, Information Technology, Low Latency, Hardware Acceleration
- **Published:** October 15, 2026
- **Apply:** https://jobs.localjobnetwork.com/apply/add/85544504/1

## About the Role

* High performance (low latency, high bandwidth) design techniques
 * Area and power-efficient complex RTL design
 * Low power microarchitecture techniques
 * Verilog RTL logic design
 * Experience with simulators and waveform debug tools
 * Knowledge of logic design principles, including timing and power implications
 * Degree in Electrical Engineering, Computer Science, or equivalent experience
 * 5 or more years of industry experience
 * Experience with IEEE floating point is a plus
 * Experience with high speed SERDES or SOC design is a plus

## Description

The Tesla AI Hardware team is looking for an ASIC RTL Design Engineer to work on industry leading AI accelerators in Palo Alto, CA. Candidate is expected to implement and document microarchitecture specifications, define system-level functional requirements, and deliver high quality design to achieve project targets.
What You'll Do

 * Micro-architecture specification and design
 * Deliver Performance, Area and Power-efficient RTL design
 * Specification, microarchitecture, and RTL design of accelerators, memory and network subsystems
 * Work with the architecture and software teams to achieve design targets
 * Balance performance, power, safety, and cost requirements
 * Trade-off functional, physical and performance requirements
 * Work with cross-functional teams, including implementation, verification, and performance engineers
 * Design for synthesis