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# Digital Design Engineer

- **Company:** Eu Recruit
- **Location:** Delft, Netherlands
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Boolean Algebra, Microarchitecture, Software Debugging, Digital Electronics, Logic Synthesis of Circuits, Perl (Programming Language), Hardware Description Language, Python (Programming Language), Micro Electro-Mechanical Systems (MEMS), Signal Processing, Static Timing Analysis, SystemVerilog, Tcl (Programming Language), Verilog, Scripting, Backend
- **Published:** May 20, 2026
- **Apply:** https://eu-recruit.com/jobs/sr-digital-design-engineer-7/

## About the Role

To address their unique technical challenges, we are looking for a strong Senior Logic Design Engineer with a solid background in key digital design and implementation areas., * Master's degree in electrical engineering

 * 5+ years of relevant work experience in the industry
 * Excellent verbal and written communication skills in English
 * Proficient in Verilog and SystemVerilog
 * Expertise in digital logic design fundamentals such as clock divider circuits, multi-clock logic designs, CDC, FIFO, FSM, etc
 * Experience in designing mixed-signal digital logic
 * Basic understanding of Discrete time Signal Processing theory, FIR, and IIR filter design
 * Solid experience in digital design flow including RTL design, synthesis, timing constraints, and STA
 * Skilled in scripting languages Perl/Tcl/Python

## Description

Our client take pride in pushing the innovation boundaries in MEMS and CMOS, using state-of-the-art analog and digital circuits to achieve very aggressive design specs for their timing solutions. Their precision timing products keep pushing the boundaries of the industry across all dimensions, continuously gaining market share., * Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD)

 * Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL
 * Developing standalone test benches to verify the RTL behavior
 * Writing and verifying SystemVerilog Assertions (SVA) for a design
 * Writing timing constraints and clock definition for synthesis and place and route tools
 * Running industry-standard synthesis tools (e.g., Genus or Design Compiler) and being able to fix timing problems if they arise
 * Understanding various design tradeoffs including timing/area/power and knowing how to improve them
 * Reading and understanding the Static Timing Analysis (STA) reports from an industry-standard STA tool (e.g., Prime Time)
 * Cross-functional interactions and communication with various teams within the organisation including analog, verification, backend, system, and test engineering teams
 * Post-Si bring-up, validation, and debugging


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