> Markdown version of [/jobs/ext/3757070-sr-dft-engineer-si-hardware](https://www.wearedevelopers.com/jobs/ext/3757070-sr-dft-engineer-si-hardware). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Sr. DFT Engineer, SI Hardware - **Company:** Tesla Motors - **Location:** Austin, TX, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Boolean Algebra, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Perl (Programming Language), Joint Test Action (IEEE Standards), Python (Programming Language), Tcl (Programming Language), Verilog, Scripting - **Published:** October 15, 2026 - **Apply:** https://jobs.localjobnetwork.com/apply/add/84799205/1 ## About the Role * Knowledge of Testability techniques and features (Compressed Scan, Built-in-Self-Test,Loop-Back, Boundary Scan) covering digital logic domain, embedded memories and PHY/IO's * Well versed in JTAG/ 1500 / 1687 networks. BSDL, ICL and PDL knowledge preferable * Expertise in ATPG, coverage analysis, and zero-delay / SDF-based pattern simulations. Experience with Cadence DFT tools (Modus and Genus) or Mentor DFT tools (Tessent Shell) preferred * Goodknowledge of Verilog,logic design, circuit design fundamentalsas well as timing * Working knowledge of TCL, python (or another scripting language like Perl) * Experience in implementation of MBISTand knowledge of repair schemes, algorithmsis a plus * Experience or working knowledge of SERDES, Analog /mixed-signal DFT techniques (like IOBIST,loop-backsetc.) is a plus * Post Silicon experience in Pattern conversion for Testers, PatternBring-up& Debug, SiliconCharacterization etc. is a plus * Degreein Computer Engineering or Electrical Engineering orequivalent experience with evidence of exceptional abilities