> Markdown version of [/jobs/ext/3760793-staff-dft-architecture-rtl-engineer-si-hardware](https://www.wearedevelopers.com/jobs/ext/3760793-staff-dft-architecture-rtl-engineer-si-hardware). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# Staff DFT Architecture & RTL Engineer, SI Hardware

- **Company:** Tesla Motors
- **Location:** Palo Alto, CA, United States
- **Experience:** Expert
- **Salary:** $128,000.0 - $312,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Code Coverage, Computer Engineering, Joint Test Action (IEEE Standards), Machine Learning, Network Architecture, Application Specific Integrated Circuits, Hardware Acceleration
- **Published:** October 15, 2026
- **Apply:** https://jobs.localjobnetwork.com/apply/add/86923721/1

## About the Role

* Degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience
 * 10+ years of DFT architecture and RTL insertion experience on complex SoCs
 * Expert-levelproficiencywith SiemensTessentsuite (Shell,TestKompress,MemoryBIST)
 * Deepexpertisein ISTC, SSN, OCC, compression logic, and memory BIST architectures
 * Strong command of IEEE 1149.1/1149.6, 1500, and 1687 - BSDL, ICL, and PDL
 * Hands-on CDC/RDC analysis usingSpyGlass,JasperGold, or Questa CDC
 * Ability to use agentic AI flows to scale DFT insertion and validation workflows
 * Preferred
 * DFT architecture ownership on server-class or AI accelerator SoCs
 * Experience with hierarchical DFT for multi-die or 3D IC designs
 * Exposure to low-power DFT - multi-Vddand state retention considerations

## Description

Tesla's AI hardware team isseekinga highly motivated ASIC RTL Design Engineer with a specialization in the mathematical and computational aspects of custom AI accelerators. You will focus on designing high-performance, power-efficient RTL for math-intensive components that power our AI training and inference systems. This role emphasizesexpertisein tensor operations, matrix computations, and optimized data paths for advanced AI workloads.This role is located in Palo Alto, CA or Austin, TX. If you are passionate about pushing the boundaries of low-precision arithmetic, quantization techniques, and hardware acceleration for machine learning, this is your opportunity to contribute to revolutionary AI hardware.
Our Silicon Engineering team designs highly testable SoCs that meet quality and coverage targets from day one of silicon. As a Staff DFT Arch & RTL Engineer, you will define the comprehensive DFT architecture and own RTL insertion of all test structures - from scan and MBIST to JTAG and OCC - setting the foundation for full-chip test coverage and bring-up readiness.
What You'll Do

 * Define and implement full DFT architecture for complex SoC designs - ISTC, IJTAG, scan, MBIST, BISR, and JTAG boundary scan (IEEE 1149.1 / 1149.6)
 * Drive RTL insertion and integration ofTessent-based DFT structures - ISTC, SSN, OCC, compression logic, and memory BIST
 * Understanding and familiarity of hybrid bond testing
 * Perform CDC/RDC checks usingSpyGlass,JasperGold, or Questa CDC -identifyand resolve clock and reset domain crossing violations
 * Execute static verification flows - LINT checks, coding standard compliance, and design rule verification to ensure RTL quality and synthesizability
 * Own JTAG/1500/1687 network architecture - implement BSDL, ICL, and PDL specifications
 * Define and resolve DFT rule violations to ensure DFT-friendly RTL across the design
 * Leverage agentic AI flows to automate DFT rule checking, RTL insertion validation, and coverage analysis