> Markdown version of [/jobs/ext/3762195-sr-soc-rtl-design-engineer-si-hardware](https://www.wearedevelopers.com/jobs/ext/3762195-sr-soc-rtl-design-engineer-si-hardware). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Sr. SoC RTL Design Engineer, SI Hardware - **Company:** Tesla Motors - **Location:** Austin, TX, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Computer Networks, Python (Programming Language), PCI Express, Software Requirements Analysis, SystemVerilog, Tcl (Programming Language), Verilog, Scripting, Information Technology - **Published:** October 15, 2026 - **Apply:** https://jobs.localjobnetwork.com/apply/add/84799213/1 ## About the Role * Deep knowledge of SoC architecture and AXI/CHI interconnects * Optimize area and power with efficient microarchitecture methods * Proficient in Verilog/SystemVerilog and scripting languages (e.g., Python, TCL) * Skilled with simulation platforms and waveformdebug tools * Strong grasp of logicdesign principles, timing and power implications * Degree in Electrical Engineering, Computer Science, or equivalent experience * Minimum5years of industry SoC RTL design experience * Experience with IEEE floatingpoint, highspeed SERDES, SMMU, GPU or PCIe is a plus ## Description * Deliver functional IP blocks into the target SoC, ensuring they meet all architectural and software requirements * Evaluate existing internal and external IP to understand functionality, interfaces, and integration constraints * Analyze and optimize timing, performance, power, and area (PPA) across the design * Diagnose and resolve clocktree and resetdistribution issues to guarantee robust system operation * Specify, microarchitect, and RTLcode accelerators, memory subsystems, and network components * Balance tradeoffs among functional, physical, and performance targets, making datadriven decisions * Partner with crossfunctional teams (implementation, verification, performance engineering) throughout the design flow * Design for synthesis readiness, adhering to bestpractice coding styles and tool constraints