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# DFT Implementation Engineer

- **Company:** Intel Corporation
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Salary:** $141,910.0 - $200,340.0
- **Contract:** Permanent contract
- **Skills:** Adobe InDesign, Bioinformatics, Code Coverage, Computer Engineering, Logic Synthesis of Circuits, Electronic Design Automation, Perl (Programming Language), Hardware Description Language, Joint Test Action (IEEE Standards), Python (Programming Language), System on a Chip, SystemVerilog, Tcl (Programming Language), Strategies of Testing, Verilog, VHSIC Hardware Description Language (VHDL), Scripting, Application Specific Integrated Circuits
- **Published:** October 16, 2026
- **Apply:** https://www.juju.com/job/1_ScrapingHub22000-JR0285490

## About the Role

production on automatic test equipment (ATE). - Collaborate with post-silicon and manufacturing teams to verify features on silicon and document learnings for continuous improvement. - Drive high test coverage through structural and IP-specific tests to achieve product quality and defect-per-million (DPM) objectives. **Qualifications:** **Minimum Qualifications** Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field 5+ years of experience in DFT, SoC design, or related semiconductor design areas Tessent Shell flows and SSN methodology Hands-on experience with ATPG, scan insertion, and/or MBIST/repair RTL design experience using hardware description languages such as Verilog, VHDL, or SystemVerilog **Preferred Qualifications** Tessent Fast IO, ISTK, and related methodologies Exposure to or interest in large ASIC applications in design or test Familiarity with advanced DFT techniques for low-power and high-performance SoC designs Understanding of industry
standards such as IEEE 1687 (IJTAG), IEEE 1149.1 (JTAG), IEEE 1500 (Core Test), and IEEE 1838 Experience with industry-standard DFT tools such as Siemens EDA (Mentor) Tessent, Synopsys DFT Compiler, or Cadence Modus Proficiency in scripting languages such as TCL, Perl, or Python for design automation Knowledge of timing constraints, UPF, and low-power design and test methodologies Experience working across cross-functional teams or contributing to complex SoC projects Take the next step in your career journey by joining Intel's innovative team.
Start driving meaningful change in the world of technology today. **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Texas, Austin **Additional Locations:** **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits** We offer a total compensation package that ranks among the best in the industry.

## Description

**Job Details:** **Job Description:** **The Role and Impact** As a DFT Design Engineer, you will play a pivotal role in shaping Intel's silicon solutions.
Your contributions will directly influence the quality and efficiency of Intel's products, ensuring seamless integration of Design for Test (DFT) capabilities in cutting-edge designs.
This role offers the opportunity to collaborate with architecture, design, verification, and manufacturing teams, contributing to the creation of industry-leading SoC and IP solutions.
Your work will drive innovation, enhance test coverage, and optimize the power, performance, and area of complex designs, enabling Intel's leadership in silicon design and manufacturing. **Key Responsibilities** - Develop logic design and register transfer level (RTL) coding to support DFT features such as SCAN, MBIST, and BSCAN. - Provide timing closure support and test content generation for manufacturing. - Collaborate in defining architecture and microarchitecture features for blocks, subsystems, and SoCs under DFT. - Optimize designs to meet power, performance, area, timing, and test coverage goals while adhering to design integrity standards. - Write, integrate, and verify RTL and structural code for DFT functionality. - Drive verification efforts to ensure architecture and microarchitecture specifications are achieved. - Support IP and SoC integration to ensure high-quality implementation of DFT blocks. - Develop high-volume manufacturing (HVM) content for rapid bring-up and