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# Hardware ASIC Packaging SI/PI Simulation and Design Lead (Remote)

- **Company:** Cisco Systems, Inc.
- **Location:** Denver, CO, United States
- **Experience:** Expert
- **Salary:** $186,900.0 - $267,700.0
- **Contract:** Permanent contract
- **Skills:** Network Analysis, Electronic Design Automation, Signal Integrity, Performance Testing, Application Specific Integrated Circuits, Hfss, Physical Design, Ansys, Cisco
- **Published:** October 16, 2026
- **Apply:** https://www.denverjobsite.com/job.asp?id=3451674642&tx=DT10596UYT&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 6+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 3+ years of relevant signal and power integrity experience.
 * High-Speed Design & Theory: Experience with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction.
 * SI/PI Simulation Proficiency: Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS.
 * Layout Review & Physical Validation: Experience conducting detailed layout reviews and physical design validation using tools such as Cadence APD and Ansys EM flows to ensure signal performance and crosstalk mitigation.
 * Circuit Analysis: Experience with SPICE for circuit-level analysis, signal modeling, and performance validation., * Skilled in articulating ideas and technical concepts to diverse audiences, both verbally and in writing.
 * Experience with high-bandwidth memory (HBM) or high-speed memory interface SI.
 * Experience with die-to-die interfaces (UCIe or proprietary).
 * Experience with advanced packaging (CoWoS, EMIB, interposer-based designs), including SI/PI analysis of 2.5D ASIC packaging.
 * Experience with Vector Network Analysis.
 * Experience with IBIS.

## Description

We are seeking a highly qualified Signal and Power Integrity Technical Lead to help us develop our next generation ASIC packaging to help define, design and verify ASIC packaging to be deployed in a range of Cisco platforms.

 * Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
 * Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
 * Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
 * Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
 * Define the processes, methods, and tools for the design and implementation of complex ASIC/package developments.
 * Lead or participate in chip architecture discussions and the definition, architecture, and design of high-performance ASICs, including reviews of intricate IC and analog/mixed-signal circuit designs.
 * Mentor and support the signal integrity team, junior engineers, and influence packaging/hardware teams, ensuring all technical specifications and innovative solutions are met.
 * Develop and promote a culture of design reviews, postmortems, and continuous improvement across multi-disciplined engineering teams.