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# DFT Engineer (Design for Testability) - Staff

- **Company:** Micron's People Organization
- **Location:** Richardson, TX, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Code Coverage, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Dynamic Random-Access Memory, Joint Test Action (IEEE Standards), System Testing, SystemVerilog, Systems Integration, VHSIC Hardware Description Language (VHDL), Application Specific Integrated Circuits, Large Language Models, Physical Design
- **Published:** October 16, 2026
- **Apply:** https://www.juju.com/job/1_microntech1-40535390

## About the Role

implemented and verified. + Collaborate with external partners and customers to align on custom DFT interfaces and security requirements when applicable. + Support silicon bring-up, debug, and qualification activities, including correlation between design intent and manufacturing test results. **Minimum Qualifications:** + Bachelor's degree or Master's degree or equivalent experience in Electrical Engineering, Computer Engineering, or related field. + Strong fundamentals in digital design and DFT concepts (scan, MBIST, boundary scan, JTAG). + Experience with RTL design (SystemVerilog/VHDL) and logic integration. + Familiarity with semiconductor test flows from wafer probe through final test. + 5+ years DRAM or ASIC DFT Design or Verification experience. **Preferred Qualifications:** + Experience with HBM, DRAM, or advanced memory products. + Knowledge of TSV-based 3D integration and stacked-die test challenges. + Hands-on experience with at-speed test, compression, or advanced DFT
methodologies. + Exposure to DFT security, customer-specific DFT interfaces, or custom test modes. + Structured problem-solving and debug perspective. (LLM) As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth.

## Description

**Our vision is to transform how the world uses information to enrich life for** **_all_** **.** Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next generation High Bandwidth Memory (HBM) architectures and circuit blocks.
The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test (DFT) architectures for next generation High Bandwidth Memory (HBM) products.
This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test stages while balancing performance, power, area, and manufacturing cost.
The engineer works in a multi-functional manner with HBM build, verification, product engineering, test enablement, packaging, and external partners to deliver manufacturable, high quality HBM solutions. **Responsibilities will include, but are not limited to:** + Define and implement HBM DFT architectures, including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at-speed test structures. + Develop DFT solutions for both base die and DRAM die, considering stacked-die and cube-level test requirements. + Design and integrate test access mechanisms to support wafer probe, cube test, and SiP/system test flows. + Collaborate with Product Engineering and Test Enablement teams to align DFT features with manufacturing test flows and cost targets. + Support yield learning, failure analysis, and debug by enabling observability and controllability in silicon. + Work closely with logic, analog, layout, verification, and physical design teams to ensure DFT is correctly