> Markdown version of [/jobs/ext/3779394-application-engineer-architect-sta-signoff](https://www.wearedevelopers.com/jobs/ext/3779394-application-engineer-architect-sta-signoff). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Application Engineer Architect (STA SignOff) - **Company:** Cadence Design Systems, Inc. - **Location:** Seattle, WA, United States - **Salary:** $154,000.0 - $286,000.0 - **Contract:** Permanent contract - **Skills:** Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Perl (Programming Language), Python (Programming Language), Tcl (Programming Language) - **Published:** October 16, 2026 - **Apply:** https://dejobs.org/x/x/CA30062CADFA455F8A25A77C6179E1D4/job/ ## About the Role * 15+ years of experience in IC design implementation and signoff, with demonstrated success in managing large-scale technical programs. * BS/MS in Electrical Engineering, Computer Engineering, or related field. * Deep expertise in digital design fundamentals, advanced node STA & ECOs (3nm and below), and EDA tool ecosystems. * Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions * Proven track record of leading technical teams and driving customer success at executive levels. * Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure. * Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders. * Prior experience with Cadence tools (Tempus, Certus, QRC) and competitive solutions highly desirable. ## Description * Technical Expertise: Lead technical engagements with customers and partners to drive & adoption of Cadence signoff portfolio. Work closely with design teams to meet customer success metrics, guide adoption of Cadence's timing signoff & closure and AgenticAI features across advanced nodes (5nm and below). * Cross-Functional Collaboration: Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements. * Innovation & Enablement: Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for timing sigoff & closure, STA, IR Drop, and power/timing closure. * Thought Leadership: Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.