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# Senior Principal FPGA/ASIC Engineer (Onsite)

- **Company:** RTX
- **Location:** El Segundo, CA, United States
- **Experience:** Expert
- **Salary:** $145,600.0 - $276,800.0
- **Contract:** Permanent contract
- **Skills:** Unix, C++ (Programming Language), Code Coverage, Perl (Programming Language), Field-Programmable Gate Array (FPGA), Subversion, SystemVerilog, Test Case, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Scripting, Application Specific Integrated Circuits, Git, Software Version Control
- **Published:** October 16, 2026
- **Apply:** https://globalhr.wd5.myworkdayjobs.com/REC_RTX_Ext_Gateway/job/US-CA-EL-SEGUNDO-E04--2006-E-El-Segundo-Blvd--BLDG-E04/Senior-Principal-FPGA-ASIC-Engineer--Onsite-_01882345-1

## About the Role

Active and transferable U.S. government issued security clearance is required prior to start date. U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance, * RTL coding and simulation in VHDL or Verilog

 * Testbench development for the verification of RTL blocks using VHDL and/or SystemVerilog
 * Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog
 * Familiarity with revision control concepts and tools (e.g. Git, Subversion)
 * Ability to work with minimal supervision as a part of a team of engineers with a variety of skills and backgrounds while being matrixed into projects with aggressive schedules and frequent milestones
 * Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 10 years prior relevant experience or an Advanced Degree in a related field and minimum 7 years of experience

 * Active and transferable U.S. government issued security clearance is required prior to start date
 * U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance

Qualifications We Prefer:

 * Strong oral and written communication skills with the ability to document and present one's work and status

 * FPGA lab validation with advanced lab equipment
 * Design for Test (DFT) and manufacturability issues
 * Experience with Unix, scripting, C/C++, and/or Perl
 * Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Questasim, Synplify, Quartus, Vivado, or other FPGA-specific tools)

## Description

* Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking
 * Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
 * Recommend new tools and practices for continuous improvement in the group's FPGA verification flow
 * Contribute to engineering estimates for new program pursuits.
 * Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status

What You will learn:

 * You will work with an experienced team to learn best practices and Collins' engineering processes for implementing world class FPGA solutions.
 * You will get to work with cutting edge technologies developed both in house and by external vendors.