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# High Performance Compute Responsible Engineer

- **Company:** Relativity Space, Inc.
- **Location:** Long Beach, CA, United States
- **Experience:** Expert
- **Salary:** $175,000.0 - $263,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Data Centers, Software Debugging, Ethernet, Firmware, Network Planning and Design, PCI Express, Schematic Capture, Serial Communications, Signal Integrity, Data Processing, High Performance Computing, Machine Learning Operations, Pcb Layout
- **Published:** October 16, 2026
- **Apply:** https://www.thejobnetwork.com/job/b173d41e-efaa-4875-9467-29f24ca59a8f/high-performance-compute-responsible-engineer

## About the Role

* BSEE with 5+ years designing and bringing up high-speed digital compute boards, ideally with direct exposure to GPU, HPC, or modern accelerator platforms
 * Proficient in high-speed digital PCB design principles: multi-GHz signaling, dense BGA escape routing on high layer count stackups, and signal integrity analysis through both simulation and measurement
 * Strong command of power integrity and power delivery network design, including multi-rail architectures, power management IC selection, voltage sequencing, and board-level current limiting
 * Strong working experience with high-speed serial interface design, analysis and debug, particularly PCIe Gen 4/5 topology, configuration, and Ethernet

Nice to haves but not required:

 * Experience writing basic firmware for hardware bring up and validation
 * Hands-on embedded systems debug skills that let you move between careful pre-fab analysis and fast, practical problem-solving on the bench
 * Experience with COTS hardware for space applications, including radiation awareness, component derating, and upset mitigation techniques (ECC memory scrubbing, watchdog/reset architectures)
 * Hands-on experience with physical PCB layout, particularly for complex, high-layer-count boards with dense BGA packages
 * Familiarity with thermal management at the board and system level, including junction temperature modeling, thermal interface material selection, and collaborating with mechanical engineers on packaging solutions for high-TDP modules

## Description

You'll own the compute hardware from architecture through bring up - there's no hand-off to another team mid-stream. You pick the components, you design the board, you're the one powering it on and debugging it with the software team

 * Design the compute boards that deliver 10 TFLOPS of processing power for onboard AI/ML inference and science data processing within the Relay Data Center, owning the hardware from schematic capture through board-level validation
 * Architect and implement power delivery networks for high-complexity carrier boards, including 500W+ multi-rail designs with tight sequencing integrating GPU or CPU compute modules onto custom PCBs with high-speed coherent interconnects
 * Define thermal interface requirements (power dissipation budgets, junction temperature limits, interface material selection) and hand off specifications to the mechanical team, who own the thermal and packaging solution
 * Design and validate high-speed memory interfaces (HBM, DDR5), PCIe Gen 4/5 chip-to-chip links, and 10 GbE+ Ethernet connections to the payload network, along with board-level power monitoring, current limiting, and radiation upset recovery circuitry
 * Lead hardware bringup and board-level validation. Diagnose and resolve issues hands-on while collaborating closely with the software engineers who are building the software environment on top of your hardware