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# Quantum Systems Digital Design Engineer II

- **Company:** Microsoft
- **Location:** Redmond, WA, United States
- **Salary:** $102,100.0 - $202,200.0
- **Contract:** Permanent contract
- **Skills:** Microsoft Windows, Microsoft Online Services, C++ (Programming Language), Code Review, Computer Engineering, Software Debugging, Linux, Logic Synthesis of Circuits, Microprocessors, Ethernet, Firmware, Formal Verification, Field-Programmable Gate Array (FPGA), Python (Programming Language), PCI Express, Azure DevOps Pipelines, Signal Processing, Verification and Validation (Software), Specman, Static Timing Analysis, Subsystems, Systems Architecture, SystemVerilog, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Graphics Processing Unit (GPU), Git, Low Latency
- **Published:** October 17, 2026
- **Apply:** https://www.juju.com/job/1_microsoftcorp9-1970393556972164

## About the Role

constrained-random tests (SV/UVM or equivalent), build on-board diagnostics (ILA/ChipScope), and execute lab bring-up with scopes, VNAs, LA/SC, and RF instruments. + Tool flow & CI: own synthesis/implementation (Vivado/Vitis or Quartus/Prime), timing sign-off, and reproducible, scripted builds (Tcl/Python) integrated with Git/Azure DevOps CI/CD. + Quality & documentation: produce clear design docs, interface specs, and bring-up guides; participate in rigorous code/design reviews and post-silicon/post-fabrication retros. + Embody our Culture (https://microsoft.sharepoint.com/sites/Culture) and Values (https://microsoft.sharepoint.com/sites/Values) **Qualifications** **Required** + Master's Degree in Physics, Electrical/Computer Engineering, or related field AND 1+ years experience in industry or in a research and development environment + OR Bachelor's Degree in Physics, Electrical/Computer Engineering, or related field AND 2+ years experience in industry or in a research
and development environment + OR equivalent experience. + This position requires verification of citizenship or other protected status to meet legal requirements of the role.
If the role requires US citizenship, as indicated in the job description, a valid US passport must be provided to verify your citizenship.
If the role requires US Person status, as indicated in the job description, US citizens must provide a valid US passport for verification while lawful permanent residents, refugees, and asylees may complete this verification using green cards or other status documents, as applicable. **Additional or Preferred Qualifications** + 3+ years building production FPGA designs in Verilog/SystemVerilog (or VHDL), including synthesis, P&R, and static timing analysis on Xilinx/AMD (UltraScale+/Versal/RFSoC) and/or Intel platforms. + Proven delivery of low-latency, streaming datapaths (DSP, filtering, classification, or decoder-like pipelines) with tight timing closure at high clocks. + Hands-on with high-speed I/O and protocols: AXI4/AXIS, JESD204(B/C), Aurora, multi-gig SERDES; competent in link bring-up, eye margins, and error budget analysis. + Proficiency in clocking/CDC fundamentals and experience with multi-clock, multi-reset systems. +
Verification skills (simulation, assertions, testbenches; UVM a plus) and lab debug using ILA/ChipScope, scopes, LA, and RF test gear. + Familiarity with RFSoC architectures (data converters, JESD links) and/or heterogeneous co-processing with CPUs/GPUs. + Comfort working across HW/SW boundaries (DMA perf tuning, drivers, gRPC/REST control surfaces, telemetry/observability) and with scientific instrumentation. + Experience accelerating decoders (e.g., graph/union-find/MWPM-style or LDPC-class techniques), streaming inference/classification, or similar real-time algorithms. + Exposure to HLS (C/C++/HLS kernels) and mixed HLS/RTL systems; formal verification. + Background in signal processing/control or quantum control/readout concepts (nice to have; curiosity and fast learning are more important). + Experience with Windows & Linux, VS Code, Git/GitHub, Azure DevOps CI/CD; scripted builds (Tcl/Python); design docs + code reviews +
comprehensive testing are part of our quality bar. **Other Requirements** + Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.
These requirements include, but are not limited to the following specialized security screenings: + Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. + Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR), the EU Dual Use Regulation, and/or other export control regulations.

## Description

For more information about our team, visit https://www.microsoft.com/en-us/quantum . **Responsibilities** + Design & implement RTL for streaming, low-latency pipelines (e.g., readout classifiers, syndrome aggregation, and QEC decoder kernels) in Verilog/SystemVerilog, including resource/performance trade-offs and power/thermal considerations. + Design and implement high-speed interconnects between subsystems (AXI4/AXI-Stream, JESD204(B/C), Aurora, Ethernet/UDP, PCIe), including SERDES configuration, link bring-up, and throughput/latency tuning. + Design robust clocking & CDC strategies (MMCM/PLL trees, jitter budgets, multi-domain timing closure, async FIFOs, metastability analysis) for deterministic performance. + Co-design hardware/firmware/software boundaries (register maps, DMA, interrupt models, driver interfaces) with control/readout software and instrument teams; contribute to system-level design reviews. + Verification and validation: develop simulation and