> Markdown version of [/jobs/ext/3822294-rtl2gds-product-engineering-architect](https://www.wearedevelopers.com/jobs/ext/3822294-rtl2gds-product-engineering-architect). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # RTL2GDS, Product Engineering Architect - **Company:** Cadence Design Systems, Inc. - **Location:** San Jose, CA, United States - **Experience:** Expert - **Salary:** $178,500.0 - $331,500.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Very-Large-Scale Integration, Electronic Design Automation, Software Tools, Static Timing Analysis, Scripting, Application Specific Integrated Circuits, Physical Design - **Published:** October 18, 2026 - **Apply:** https://dejobs.org/x/x/47C4F06010254F0D8DD3E5DB010CA6BE/job/ ## About the Role * BS in Electrical Engineering with at least seven years of experience in digital implementation as either a design or product engineer * Candidates should demonstrate a solid understanding of VLSI physical design and timing analysis, including familiarity with clock tree synthesis, routing optimization, and silicon signoff challenges * Experience with industry-standard EDA tools for synthesis, physical design, and signoff at 7nm and below nodes is required * Proficiency in scripting languages or AI tools for productivity enhancement will be considered an asset * Strong verbal and written communication skills ## Description This position presents an exciting opportunity within Cadence's Digital and Signoff Group (DSG) for a Product Engineer. In this dynamic environment, you'll collaborate closely with R&D, Application Engineering & product marketing teams to help drive the development of advanced chip design software tools. As a Product Engineer, you will serve as a key technical resource, providing place-and-route expertise to both Cadence customers and internal development teams. Candidates should bring a strong motivation and energy, along with a thorough understanding of ASIC design methodologies across all stages of the RTL to GDSII flow. Hands-on experience with timing closure and PPA optimization at 7nm and below is essential. Your analytical strengths will be vital in diagnosing customer challenges and delivering well-organized solutions. Excellent communication skills are required to ensure clear and effective collaboration. Responsibilities for this role include supporting Cadence's digital products, tracking and resolving customer issues alongside R&D and release teams, and conducting design benchmarks. You will also develop innovative flows and methodologies tailored to customer needs.