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# Senior Emulation Performance Methodology & Debug Engineer

- **Company:** Qualcomm
- **Location:** Austin, TX, United States (Remote available)
- **Experience:** Expert
- **Salary:** $121,800.0 - $182,600.0
- **Contract:** Permanent contract
- **Skills:** C (Programming Language), Software Debugging, Digital Electronics, Emulators, Field-Programmable Gate Array (FPGA), Joint Test Action (IEEE Standards), Python (Programming Language), Kernel Debuggers, SystemVerilog, Tcl (Programming Language), Verilog, Scripting, Application Specific Integrated Circuits
- **Published:** October 18, 2026
- **Apply:** https://www.indeed.com/viewjob?jk=60ec4be883f94c5c

## About the Role

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Preferred Requirements:

5+ years of experience working in emulation and silicon environments., 5+ years of experience working in emulation and silicon environments. Candidates are expected to have experience in:

 * Design, development, and deployment of uniform global methodologies for emulation build generation and debug across FPGA based emulation platforms of various configurations
 * Cross-site collaboration, vendor engagements, and executive communication
 * Pre-silicon prototyping for new SoC designs, including pre-silicon enablement and bring-up
 * Bring-up of new FPGA emulation/prototyping hardware and software
 * Debugging low level software and hardware issues
 * Debug tools including JTAG and kernel debuggers
 * Validation and debug of digital circuits
 * CPU and SoC architectures, with solid understanding of SoC building blocks (interconnects, power management, PMIC, NoC, peripherals)
 * Basic understanding of power and performance
 * Expertise in Verilog / SystemVerilog
 * Experience with C programming
 * Scripting: Proficient in Python, TCL
 * FPGA Expertise: Xilinx/Intel FPGAs, Tools, and timing closure techniques, * Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience., Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.