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# PreSilicon Power Modeling Leader - x86 SoCs

- **Company:** Advanced Micro Devices, Inc.
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Salary:** $178,400.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, BIOS, Microarchitecture, Python (Programming Language), Regression Analysis, SystemC, Grafana, Caching, Perf (Linux), Influxdb, Physical Design, Jenkins
- **Published:** October 18, 2026
- **Apply:** https://diversityjobs.com/career/15479870/Senior-Staff-Presilicon-Power-Modeling-Lead-X86-Socs-Texas-Austin

## About the Role

* Demonstrated experience building toplevel SoC power models with high correlation to silicon, including IPlevel VBM integration and workloadbased projections.
 * Handson with EDA/tooling: PowerArtist, PrimeTime PX (or equivalents), activity annotation (FSDB/VCD), UPF/CPF power intent, Python for automation.
 * Deep knowledge of x86 microarchitecture (CPU pipelines, caches), GPU/NPU basics, memory subsystems, interconnect/fabric behavior, and power delivery/PDN interactions.
 * Proven ability to define DVFS/AVFS strategies and drive FW telemetry requirements; familiarity with EDC/TDC/CaC semantics and their impact on power.
 * A validated SoC power model & scorecard that anchors program power budgets and executive reviews.
 * Workloadspecific DVFS/AVFS tables and telemetry specs for FW/BIOS enablement.
 * Correlation reports (estimated vs. measured) and recommendations that accelerate firsttimeright silicon.
*, * Segment experience modeling power for automotive (AECQ100/ASIL) usecases, networking throughput workloads, storage I/O patterns, industrial/robotics duty cycles.

 * System performance modeling familiarity (GEM5/Simics/SystemC) to align Perf/Watt predictions and bottleneck analysis with architecture teams.
 * Experience creating PnP dashboards/regressions (Python/Jenkins/Grafana/InfluxDB) for continuous tracking., * B.S./M.S. in EE/CE/CS (or related) with strong industry experience in SoC presilicon power modeling/estimation and crossdomain collaboration.

## Description

AMD's embedded and client x86 programs demand firsttimeright silicon. You will lead SoClevel presilicon power modeling-owning the methodology, models, and crossfunctional influence that translate into accurate Perf/Watt projections, robust DVFS/AVFS plans, and silicon correlation that derisks program power budgets., * Own the SoC power model endtoend using AMD's converged methodology, delivering accurate workloadbased power estimates for CPU/GPU/NPU, fabric/interconnect, memory, and I/O.

 * Define usecase power envelopes across automotive, networking, storage, industrial, and robotics segments; partner with product/marketing to derive representative workloads and KPIs.
 * Drive DVFS/AVFS strategy (Pstates, Cstates, voltage/frequency points), telemetry requirements, and FW handoffs based on model outputs; provide early tables and guardrails to FW/BIOS.
 * Establish IP/subsystem power budgets; run sensitivity studies to guide architectural decisions (e.g., cache sizes, fabric frequencies, NPU/GPU configurations).
 * Build repeatable modeltosilicon correlation plans (CaC/static/dynamic splits, EDC/TDC interactions, droop mitigation) and maintain a power scorecard for program reviews.
 * Lead tool flows & automation (e.g., PowerArtist, PrimeTime PX; Pythonbased pipelines) to ingest activity (FSDB/VCD), generate reports, and publish dashboards for stakeholders.
 * Collaborate across Architecture, RTL/Design, Physical Design, FW/BIOS, and System PnP to ensure converged Perf/Watt outcomes from concept through bringup., AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.