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# Senior ASIC RTL Engineer

- **Company:** Cisco Systems, Inc.
- **Location:** New York, NY, United States
- **Experience:** Expert
- **Salary:** $167,700.0 - $245,200.0
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Software Debugging, Formal Verification, Joint Test Action (IEEE Standards), SystemVerilog, Verilog, Application Specific Integrated Circuits, Backend, Optimization Algorithms, Code Inspection, Front End Software Development, Physical Design, Cisco
- **Published:** October 19, 2026
- **Apply:** https://diversityjobs.com/career/18681810/Senior-Asic-Rtl-Engineer-California-San-Jose

## About the Role

* Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 7 years of experience
 * Prior experience in Verilog/System Verilog coding.
 * Prior experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification).
 * Prior experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories.

Preferred Qualifications:

 * Prior experience with power optimization techniques , power intent (UPF), power estimation.
 * Prior experience with DFT/MBIST is a plus
 * Prior experience with post-silicon debug

## Description

You will be a key member of the Silicon One development organization, collaborating closely with Front-end RTL and backend physical design teams to gain a deep understanding of chip architecture. Your primary focus will be to drive high-quality Design for Test (DFT) RTL, ensuring robust and reliable silicon solutions that meet Cisco's standards for performance and innovation. This cross-functional teamwork is essential to delivering advanced networking silicon aligned with Cisco Silicon One's scalable and flexible architecture.