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# Front End RTL Designer / SoC integration

- **Company:** Jobposting
- **Location:** Belgium (Remote available)
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Computer Engineering, Software Debugging, Vim (Text Editor), SystemVerilog, Verilog, Front End Software Development, Physical Design
- **Published:** October 22, 2026
- **Apply:** https://startup.jobs/front-end-rtl-designer-soc-integration-vertical-compute-10078587

## About the Role

* Solid background and experience in front-end RTL design and top-level SoC/chiplet integration.
 * Degree (B.S., M.S., or Ph.D.) in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
 * Strong hard skills in RTL languages (SystemVerilog/Verilog), IP integration, and working closely with verification and physical design teams to optimize PPA (Power, Performance, Area).
 * Strong communication and collaborative problem-solving skills in a fast-paced environment.
 * Fluency in English with effective written and verbal communication skills.

## Description

We are looking for a Front-End RTL Designer to contribute to building our Vertical Compute's 3D-integrated chiplets. In this role, you will focus on top-level integration and integrating all IPs to build the AI accelerator that will demonstrate the full potential of our Vertical Integrated Memory (VIM ) technology. You will handle full SoC integration, working in close collaboration with verification and physical design teams to ensure the targeted Power, Performance, and Area (PPA) of the product., * Lead top-level SoC and chiplet integration, incorporating all internal and third-party IPs to build high-performance AI accelerators.

 * Integrate proprietary Vertical Integrated Memory (VIM ) technology with compute engines to maximize throughput and bandwidth efficiency.
 * Partner closely with functional verification teams to build verification environments, debug RTL issues, and ensure robust design coverage.
 * Collaborate with physical design teams to optimize Power, Performance, and Area (PPA), supporting synthesis, timing closure, and floorplanning.

About the team:

This role is part of the Hardware (HW) team, reporting directly to the HW Manager. You will join a collaborative and innovative team dedicated to delivering cutting-edge AI accelerator solutions and pushing the boundaries of memory and compute integration.