> Markdown version of [/jobs/ext/3868116-asic-research-engineer-front-end-digital-design](https://www.wearedevelopers.com/jobs/ext/3868116-asic-research-engineer-front-end-digital-design). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # ASIC Research Engineer- Front-End Digital Design - **Company:** University of South Carolina - **Location:** Arlington, VA, United States - **Experience:** Experienced - **Salary:** $115,000.0 - $140,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Computer Engineering, Microarchitecture, Linux, Digital Arts, Logic Synthesis of Circuits, Microprocessors, Electronic Design Automation, Field-Programmable Gate Array (FPGA), Hardware Design, Machine Learning, Tensorflow, Signal Processing, SystemVerilog, Verilog, VHSIC Hardware Description Language (VHDL), Scripting, Application Specific Integrated Circuits, Pytorch, Deep Learning, HuggingFace, Integration Frameworks, Front End Software Development, Software Version Control - **Published:** October 22, 2026 - **Apply:** https://usc.wd5.myworkdayjobs.com/ExternalUSCCareers/job/Arlington-VA/ASIC-Research-Engineer--Front-End-Digital-Design_REQ20182054 ## About the Role * Ability to handle Controlled Unclassified Information (CUI). Per U.S. government regulations, eligibility to handle CUI requires U.S. Citizenship or Permanent Residency. * Degree in Computer Engineering, Electrical Engineering, or related field * Bachelor's degree with >3 years of experience, or Master's degree * Demonstrated excellence creating digital designs with Verilog, System Verilog, or VHDL RTL * Solid understanding of computer architecture and microarchitecture * Demonstrated skills with EDA tools, scripting, revision control, * Experience using logic synthesis and timing tools * Familiarity with digital design verification * Familiarity with performance modeling * Familiarity with agile hardware design methodologies * Experience with AI-assisted workflows * Experience using FPGAs * Effective at verbal communication and giving clear explanations The annual base salary range for this position is $115,000 to $140,000. When extending an offer of employment, the University of Southern California considers factors such as (but not limited to) the scope and responsibilities of the position, the candidate's work experience, education/training, key skills, internal peer equity, federal, state, and local laws, contractual stipulations, grant funding, as well as external market and organizational considerations., Minimum Education: Bachelor's degree, combined experience/education as substitute for minimum education Minimum Experience: 3 years Preferred Education: Master's degree Preferred Experience: 5 years Required Skills: Experience with Linux. Preferred Skills: Proven leadership ability. Experience with artificial intelligence, very large-scale integration design, machine learning, deep learning (e.g., TensorFlow, PyTorch, HuggingFace), and Dockerization. ## Description ISI's CS&T Division has an opening in Arlington, VA for an ASIC Research Engineer - Front-end Digital Design, to perform digital design of advanced ASIC prototypes addressing problems of national importance. The Engineer will work with a cutting-edge team to design and verify register-transfer level (RTL) models of CPUs, memories, and accelerators for applications such as communications, signal processing, and security. The Engineer will have opportunities to collaborate with ISI's MOSIS 2.0 service, integrate third-party IP cores, and gain experience working with top research sponsors such as DARPA, IARPA, and the CHIPS Act. The position provides a collaborative, flexible university setting with rich learning and growth opportunities. The Engineer will gain experience in a fast-moving research setting and work toward a better and more secure future.