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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Research Computer Scientist, Reconfigurable Computer Architecture - **Company:** University of South Carolina - **Location:** Arlington, VA, United States - **Salary:** $140,000.0 - $180,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, C++ (Programming Language), Encodings, Computer Engineering, Extract Transform Load (ETL), Digital Electronics, Field-Programmable Gate Array (FPGA), Hardware Description Language, Hardware Design, Python (Programming Language), Reduced Instruction Set Computing, Signal Processing, SystemVerilog, Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Application Specific Integrated Circuits, Software Verification, AI Coding Agents, Information Technology, Decoding - **Published:** October 22, 2026 - **Apply:** https://usc.wd5.myworkdayjobs.com/ExternalUSCCareers/job/Arlington-VA/Research-Computer-Scientist--Reconfigurable-Computer-Architecture_REQ20182072 ## About the Role * Doctorate in computer engineering, electrical engineering, computer science, or a closely related field. * Demonstrated research contributions in computer architecture or reconfigurable computing. * Ability to reason across architecture and implementation, with experience in performance modeling, simulation, RTL design, FPGA prototyping, or related hardware development. * Proficiency in Python or C++ for architecture modeling and evaluation, and working knowledge of Verilog, VHDL, or SystemVerilog for digital hardware prototypes. * Strong technical writing, collaboration, and research leadership skills. * Ability to handle Controlled Unclassified Information (CUI). Per U.S. government regulations, eligibility to handle CUI requires U.S. citizenship or permanent residency., * Five or more years of relevant research experience. * Expertise in coarse-grained reconfigurable arrays, heterogeneous or domain-specific accelerators, RISC-V or Arm processors, high-bandwidth interconnects, high-speed I/O, or hardware-software co-design. * Experience with RF or DSP workloads, error-control coding, communication systems, ASIC development, verification, compiler or runtime integration, or sponsor-funded research. * Familiarity with FPGA and ASIC implementation and verification tools, such as Vivado, Verilator, or commercial EDA flows. * Experience applying AI coding assistants or agents to Verilog, VHDL, or SystemVerilog development, verification, or hardware design exploration. The annual base salary range for this position is $140,000 to $180,000. When extending an offer of employment, the University of Southern California considers factors such as, but not limited to, the scope and responsibilities of the position, the candidate's work experience, education and training, key skills, internal peer equity, federal, state, and local laws, contractual stipulations, grant funding, and external market and organizational considerations., Minimum Education: Doctorate Minimum Experience: <1 year Minimum Skills: Demonstrated record of outstanding research contributions and experience. Proven technical proficiency, exceptional creativity, successful collaboration with others, and independent thought. Strong managerial skills. Demonstrated reputation as an emerging leader in field with sustained performance and accomplishment. Demonstrated ability to conceptualize research directions, exert technical leadership, communicate technical ideas, coordinate individual contributions to a research program, and present research plans and results in a manner that will elicit favorable funding actions. Preferred Experience: 5 years Preferred Skills: Nationally recognized reputation for excellence in area of expertise. ## Description Architecture and research Define and evolve reconfigurable architectural components, including processing elements, configurable compute fabrics, control and scheduling mechanisms, on-chip communication, memory and data movement, and interfaces to external systems. Formulate research questions and conduct trade studies involving rapid reconfiguration, determinism, throughput, energy efficiency, scalability, and programmability. Develop performance models and publishable technical results. Prototype and evaluation Lead architecture modeling, RTL and FPGA prototyping, integration, verification, and benchmarking in collaboration with hardware, compiler, software, and application researchers. Investigate AI-assisted and agent-based methods for HDL design, testbench generation, and design exploration, and verify generated artifacts against functional and performance requirements. Establish representative workloads and measurable requirements, analyze bottlenecks, and guide design changes. Support application demonstrations such as adaptive encoding and decoding workflows or multifunction RF signal processing, as program needs warrant. Technical leadership and sponsored research Provide technical direction to researchers, engineers, and students; coordinate architecture deliverables across collaborating organizations; document designs and results for sponsors; contribute to proposals, reports, publications, and presentations; and engage prospective transition partners regarding architecture requirements and evaluation.