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# Senior DRAM Systems Architecture

- **Company:** Micron Technology, Inc.
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $164,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Computer Engineering, Dynamic Random-Access Memory, Metadata, Reliability Engineering, Software Tools, Systems Architecture, System Software, Application Enhancement Tool, High Performance Computing, Large Language Models, Generative AI, Agentic-AI, Information Technology, Modeling and Simulation
- **Published:** October 23, 2026
- **Apply:** https://www.sanjosejobsite.com/job.asp?id=3466351995&tx=FJ8582FFQ&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Master's degree or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, Applied Mathematics, Physics, or a related technical field.
 * 8+ years of experience in memory systems, semiconductor architecture, computer architecture, or related technical areas.
 * Strong knowledge of DRAM architecture, memory systems, or high-performance computing system architecture.
 * Proven ability to develop architecture recommendations using quantitative analysis and engineering tradeoffs.
 * Experience using AI-powered tools and methodologies, including Large Language Models, Agentic AI, Generative AI, or AI-enabled simulation environments., * Experience working with DDR, LPDDR, HBM, CXL memory, MRDIMM/RDIMM, or emerging memory technologies.
 * Experience with memory-system simulation or modeling tools such as Ramulator, Ramulator2, DRAMsim3, gem5, internal simulators, or equivalent platforms.
 * Experience in queueing theory, stochastic modeling, performance modeling, reliability modeling, or mathematical optimization.
 * Experience with RAS architecture, ECC, CRC, EDC, metadata, on-die ECC, rank-level protection, link protection, or system-wide robustness.
 * Background in high-speed signaling, SI, clock distribution, packaging, module, PMIC, power, or thermal systems and experience participating in JEDEC or similar standards organizations.

## Description

As a Technical Staff Member, you will provide systems-level architecture leadership for next-generation memory solutions. This role combines analytical modeling, architecture development, reliability strategy, and cross-functional influence to help define future products. You will work across engineering disciplines to evaluate tradeoffs, guide technical decisions, and develop differentiated solutions that deliver value to customers and platforms., * Define architectures for DDR, LPDDR, HBM, CXL-attached memory, and emerging memory technologies.

 * Develop analytical and simulation-based models to evaluate performance, reliability, power, thermal, and cost tradeoffs.
 * Drive architecture requirements across DRAM, packaging, modules, controllers, platforms, and system software.
 * Lead technical studies, roadmap development, and architecture recommendations supported by quantitative analysis.
 * Influence cross-functional teams, mentor engineers, and contribute to patents, publications, and standards activities.