> Markdown version of [/jobs/ext/3882739-fpga-prototyping-and-emulation-engineer](https://www.wearedevelopers.com/jobs/ext/3882739-fpga-prototyping-and-emulation-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # FPGA Prototyping and Emulation Engineer - **Company:** CommonAI C.I.C. - **Location:** Cambridge, UK - **Salary:** £60,000.0 - £105,000.0 - **Contract:** Permanent contract - **Skills:** Software Debugging, Emulators, Field-Programmable Gate Array (FPGA), Hardware Description Language, SystemVerilog, Toolchain, Verilog, VHSIC Hardware Description Language (VHDL), AI Infrastructure, AI Coding Agents, Hardware Acceleration - **Published:** October 23, 2026 - **Apply:** https://www.adzuna.co.uk/jobs/details/5938018311 ## About the Role Hands-on experience taking RTL through an FPGA prototyping or emulation flow and debugging the resulting system. - Strong digital-design skills in Verilog, SystemVerilog, VHDL or an equivalent HDL, together with practical timing and verification judgement. - Experience with a relevant FPGA or emulation toolchain and the scripting needed to make builds and experiments repeatable. - The ability to collaborate across hardware and software boundaries and explain the conclusions and limitations of a prototype experiment. - Practical experience using AI coding agents, with the judgement to validate generated HDL, scripts and software. Experience with processor or accelerator designs, multi-FPGA partitioning, host interfaces or performance characterisation would be useful. Depth with a relevant platform is sufficient; the team will choose the initial platform and design around the first useful study., We particularly welcome experienced engineers and can also consider earlier-career candidates with strong evidence of ability. Relevant postgraduate study is useful, but qualifications are secondary to experience and the quality of your work. ## Description Our Scaling Inference Lab (SIL) is developing simulation grounded in real measurements to help the UK invest in promising AI infrastructure. We connect proposed hardware designs to realistic workloads, helping investors and engineers understand their potential, their limitations and the next experiment worth doing. The Opportunity Help evaluate proposed AI hardware before it is available as a finished chip. You will turn RTL designs into working FPGA prototypes and emulation experiments, giving SIL and its technology partners a practical way to explore design behaviour and architectural choices. The initial focus is on RTL prototyping and emulation. You will help choose a useful first design and platform, adapt and integrate the RTL, and establish repeatable build, bring-up and experimental workflows. Working with our partners and colleagues in software and simulation, you will connect observations from the prototypes to wider system studies. Your work will help establish what the experiments tell us about a proposed design, how those findings relate to simulator models and where further evidence is needed. What you will do - Adapt and integrate RTL for FPGA prototyping or emulation, working with the design owners and documenting changes needed for the prototype. - Develop and maintain synthesis, implementation, timing-closure and reproducible build flows for the selected platform. - Bring up and debug designs, developing tests and instrumentation to check functional behaviour and support repeatable experiments. - Develop or integrate the control, stimulus and data-capture facilities needed for the agreed experiments, working with software colleagues on host interfaces and integration. - Relate observations from emulation to the model being evaluated, explaining how prototype frequency, interface overheads and other limitations affect interpretation. - Help assess platform, toolchain and hardware requirements, and document workflows that colleagues and partners can reuse. An example early project would be to take a partner's RTL design through FPGA implementation and bring-up, then instrument it to investigate a selected architectural choice and compare observations with a simulator model.