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# Principal Embedded Firmware Engineer - AI/HPC Networking Silicon

- **Company:** Cornelis Networks
- **Location:** Boston, MA, United States (Remote available)
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, C++ (Programming Language), CMake, Code Generation, Embedded Software, Ethernet, Firmware, Python (Programming Language), Multiprocessing, Software Architecture, Quick EMUlator (QEMU), Remote Direct Memory Access, Reduced Instruction Set Computing, Secure Hash Algorithm, Toolchain, YAML, Application Specific Integrated Circuits, Integration Tests, Bare Metal
- **Published:** October 23, 2026
- **Apply:** https://www.dice.com/job-detail/38a50162-9542-4e70-9e81-8f60efdb8d58

## About the Role

* 10+ years of embedded/firmware engineering, with a track record of software architecture and technical leadership.
 * Expert C (C++ a plus) and working Python.
 * Deep experience with bare-metal firmware on constrained cores, including manually managed local memories and low level bring-up.
 * Experience with secure boot / image authentication and hardware root-of-trust integration.
 * Experience programming hardware CSRs and co-designing register-level interfaces with silicon teams.
 * Demonstrated, hands-on AI-assisted engineering proficiency, plus the judgment to validate what the AI produces.

Preferred Qualifications

 * RISC-V firmware and toolchain experience.
 * Firmware orchestration for multi-core accelerator arrays.
 * Hardware root-of-trust ecosystems (e.g., Caliptra) and SHA-2/signature verification.
 * Code-generation toolchains (SystemRDL, Kaitai, CMake) and simulator-based co-verification.
 * Familiarity with emerging AI/HPC interconnect standards: Ultra Ethernet (UEC), UALink, and ESUN.
 * Background in HPC/AI networking, RDMA, or libfabric.

## Description

Cornelis Networks builds high-performance fabric solutions for AI and HPC. We're looking for a principal-level embedded engineer to help architect firmware across our next-generation networking silicon. A key focus of the role is the management firmware that boots, secures, and controls the on-chip compute engines that accelerate collective communication (all-reduce, broadcast, reduce-scatter), alongside broader embedded architecture work across the platform. You'll own the infrastructure layer that makes these engines trustworthy and production-ready, not the collective algorithms themselves.

This role is a mixture of hands-on architecture, firmware development, technical leadership, and mentorship, with heavy use of AI tools across design, implementation, and testing., * Architect and implement bare-metal C firmware on a RISC-V management core that provisions, boots, and supervises arrays of on-chip acceleration engines.

 * Own the secure firmware-loading pipeline: fetch images from flash, coordinate hardware root-of-trust authentication, and distribute verified images into each engine's local memories through on-chip fan-out/DMA hardware.
 * Build per-engine bring-up, reset sequencing, and health validation driven by control/status registers, with solid
timeout and error handling and enforced security invariants.

 * Scale firmware distribution and bring-up across many engines and multiple dies, including runtime re-boot and in-field firmware updates.
 * Define the hardware/software contract with ASIC/RTL teams using a datamodel-first workflow (e.g., SystemRDL, Kaitai, YAML generated code).
 * Validate firmware against functional simulators (e.g., QEMU) with automated unit and integration tests.
 * Set architecture standards, review designs and code, and mentor engineers.