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# Digital Design RTL Engineer

- **Company:** Broadcom
- **Location:** Fort Collins, CO, United States
- **Experience:** Expert
- **Salary:** $121,900.0 - $195,000.0
- **Contract:** Permanent contract
- **Skills:** Logic Synthesis of Circuits, SystemVerilog, Physical Design
- **Published:** October 23, 2026
- **Apply:** https://www.techcareers.com/job.asp?id=3466359607&tx=KR6161FFI&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of PPA optimization, clock domain crossing (CDC) analysis, and low-power design techniques., * BSEE required, MSEE/PHD preferred
 * 8+ years of industry experience with a focus on SoC integration, LPDDR5/6, DDR4/5 and/or high-speed SerDes, or HBM protocols is highly preferred.

## Description

The ideal candidate has a proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of RTL Design, PPA optimization, clock domain crossing (CDC) analysis and Reset Domain crossing (RDC). Beyond technical execution, you will collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule., * Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off

 * Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule
 * High proficiency in SystemVerilog