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# Principal, MTS, DRAM Systems Architect

- **Company:** Micron Technology, Inc.
- **Location:** Boise, ID, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Dynamic Random-Access Memory, Perl (Programming Language), Python (Programming Language), Scripting, Agentic-AI
- **Published:** October 23, 2026
- **Apply:** https://www.techcareers.com/job.asp?id=3466676227&tx=KR3131FFP&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Minimum MSEE + 10 years or BSEE + 12 years of industry experience with strong background in designing high-speed IO interface, timing and clocking circuits with proven silicon successes.
 * Ability to supervise layout work and understand good layout practices for high-speed circuits to minimize parasitic impacts.
 * Strong interpersonal skills with the ability to convey sophisticated technical concepts to other design peers both verbally and written.
 * Mental agility and ability to multi-task is a must for this position as we work with all product types (commodity, mobile, graphics) and product teams in parallel with silicon validation efforts., * Prior experience in DRAM circuit design experience.
 * Prior experience in channel modeling and characterization, transceiver noise and timing budget analysis, equalization techniques, SI knowledge, etc.
 * Understanding of device physics and basic CMOS processing techniques.
 * Demonstrated ability in mentoring and coaching engineers early in their careers.
 * Demonstrated ability with AI/ML usage and fluency in scripting languages such as PERL/Python.
 * Use of Agentic AI

## Description

We are seeking a Principal/Member of Technical Staff (MTS) IO/Clock Design Engeer to join our DRAM IP Design team and contribute to the development of critical high-speed IP circuits used across Micron's DRAM memory products. In this role, you will be responsible for the design, development, optimization, verification, and technical support of these high-speed IPs. You will focus on equalization and bandwidth extension to push the limits of circuit and process performance, analyze IO impairments as well as clock jitter and duty cycle distortion, and assess their impact on DRAM system timing. You will also develop and implement effective engineering solutions to address these challenges., * Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products.

 * Apply robust high-speed circuit design techniques and enhance critical performance evaluation, including timing and jitter sensitivity, of the IO data path and clock path at circuit and full-chip level.
 * Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level.
 * Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities.
 * Collaborate with process integration and transistor modeling teams on Micron's next groundbreaking process node.
 * Work with the internal data science team and EDA vendors to leverage and improve AI-assisted design flow and circuits optimization.