> Markdown version of [/jobs/ext/3901178-rtl-design-engineer-staff-asic-design-engineer-soc-design-engineer-processor-design-engineer-or-logic-design-engineer](https://www.wearedevelopers.com/jobs/ext/3901178-rtl-design-engineer-staff-asic-design-engineer-soc-design-engineer-processor-design-engineer-or-logic-design-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # RTL Design Engineer, Staff ASIC Design Engineer, SoC Design Engineer, Processor Design Engineer or Logic Design Engineer - **Company:** IC Resources - **Location:** Eindhoven, Netherlands - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Microarchitecture, Software Debugging, Logic Synthesis of Circuits, Emulators, Field-Programmable Gate Array (FPGA), Software Engineering, SystemVerilog, Systems Integration, Verilog, Application Specific Integrated Circuits, Front End Software Development, Physical Design - **Published:** October 24, 2026 - **Apply:** https://www.careerjet.nl/job/nle0888bc1da225bd072d1a34c27ac6664/eaa ## About the Role 5+ years of ASIC / SoC RTL Design experience Strong SystemVerilog or Verilog Experience with processors, accelerators or complex SoCs Strong microarchitecture experience Experience with synthesis and timing-aware RTL design Good knowledge of AMBA / AXI / AHB / APB Strong CDC / RDC expertise Hands-on low-power design experience Gate-level simulation and debugging experience At least one successful ASIC tape-out Experience owning one or more design blocks through the development cycle ## Description Are you an experienced RTL Design Engineer who wants to work on genuinely new processor technology rather than another incremental SoC update? I'm working with a fast-growing semiconductor company in Eindhoven developing a new generation of AI compute and accelerator silicon. The team is building highly complex processor and SoC technology from the ground up, with a strong focus on performance, power efficiency and scalable AI workloads. They are now looking for a Senior / Staff Logic Design Engineer to take ownership of key RTL blocks and help turn architectural concepts into production-ready silicon. What you'll be doing You'll work across the full front-end design flow, including: Developing synthesizable SystemVerilog / Verilog RTL Translating architecture and ISA requirements into microarchitecture Designing processor, accelerator and complex SoC blocks Integrating internal and third-party IP Working closely with verification, architecture and physical design teams Supporting synthesis, timing closure and PPA optimisation Driving CDC / RDC quality and sign-off Implementing low-power techniques including clock gating, power gating and memory power management Supporting gate-level simulation, FPGA and emulation activity Taking real ownership of design blocks through to tape-out What they're looking for