> Markdown version of [/jobs/ext/3902514-early-career-soc-digital-design-engineer](https://www.wearedevelopers.com/jobs/ext/3902514-early-career-soc-digital-design-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Early Career - SoC Digital Design Engineer - **Company:** Apple Inc - **Location:** München, Germany - **Salary:** €47,500.0 - €67,500.0 - **Contract:** Permanent contract - **Skills:** C (Programming Language), C++ (Programming Language), Computer Programming, Microarchitecture, Logic Synthesis of Circuits, Perl (Programming Language), Python (Programming Language), System on a Chip, SystemVerilog, Tcl (Programming Language), Verilog, Backend, Physical Design - **Published:** October 24, 2026 - **Apply:** https://www.xing.com/jobs/muenchen-early-career-soc-digital-design-engineer-154613902 ## About the Role * You hold an MSEE. * Ability to fluently speak and write in English. * You should have some experience in silicon design * RTL coding, block-level simulations, and synthesis * Verilog / System Verilog skills Preferred Qualifications * Experience with scripting and programming languages with some of the following: Python, Perl, C, C++, and TCL is an advantage. * Familiar with the various backend tools (synthesis and STA) - an advantage. * Familiar with verification methodologies - an advantage. * Microarchitecture definitions at the unit level ## Description As a SoC Digital Design Engineer, you will have responsibilities spanning all aspects of the SoC design flow., * Work with the architecture team to develop the microarchitecture spec. * Develop RTL for one or more blocks following established design guidelines based on microarchitecture spec. * Work on sophisticated design practices (Clock/Reset/Voltage domain crossing, DFT, Low Power Design, power optimisation, and synthesis). * Work closely with the verification team on block/top level to ensure timely delivery of quality designs. * Work closely with the physical design team to optimize the design and meet design targets (area, timing, and power).