> Markdown version of [/jobs/ext/3905110-memory-design-engineer](https://www.wearedevelopers.com/jobs/ext/3905110-memory-design-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Memory Design Engineer - **Company:** intel - **Location:** UK - **Experience:** Experienced - **Salary:** £39,056 - **Contract:** Permanent contract - **Skills:** Compilers, Perl (Programming Language), Process Driven Development, Static Timing Analysis, Tcl (Programming Language), Scripting - **Published:** October 25, 2026 - **Apply:** https://www.adzuna.co.uk/jobs/details/5210483221 ## About the Role You will be part of the Corporate Memory Organization memory compiler team and will own significant engineering tasks in a fast-paced and technically challenging environment. Responsibilities would include but are not limited to: Provide design solutions for meeting challenging memory design specs for various product segments, Memory Compiler Design Flow/Methodology development, Design, validation and characterization of Memory Compilers and Interfacing with customers. Behavioral traits for this position include logical thinking, good verbal and written communication and interpersonal skills, ability to prioritize work/multitask, good analytical and problem solving skills., You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates., * Must already have a Bachelors (B.Tech) and 4 years experience or Masters (M.Tech) in Electrical Engineering and 2 years experience. * Experience with scripting (Perl, tcl etc.), * 2-4 years experience with scripting (Perl, tcl etc.) to develop a memory compiler and support or enhance the tool as required * 2-4 experience in memory design convergence tools including: formal equivalence verification, static timing methodology, electrical reliability and robustness analysis * 2-4 years experience with transistor level operation, memory bitcell design, design challenges under process variations and low power circuit techniques