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# Memory SW Engineer

- **Company:** IBM
- **Location:** UK
- **Experience:** Experienced
- **Salary:** £42,999.0
- **Contract:** Permanent contract
- **Skills:** C (Programming Language), Artificial Intelligence, IBM AIX, Apple IOS, C++ (Programming Language), Linux, Perl (Programming Language), Embedded Software, Serial ATA, Firmware, Hardware Design, Hardware Platform Interface, Python (Programming Language), PCI Express, USB, Scripting
- **Published:** October 25, 2026
- **Apply:** https://www.adzuna.co.uk/jobs/details/5210485900

## About the Role

* Bachelors/Masters In EE/CE with 3 years of directly related experience
 * 2+ years of demonstrated expertise in C++/C programming and scripting language (Python, Perl, etc)
 * Knowledge of System technologies (DDR or other High-Speed IOs such as PCIe, SATA, USB)
 * Knowledge of modern OS kernel (Linux, AIX)
 * Good written and oral communication skills, with the ability to communicate with a variety of engineering disciplines and management.

Preferred Technical And Professional Expertise

 * Demonstrated experience in using oscilloscopes and logic analyzers.
 * Demonstrated technical expertise in hardware development, Embedded software procedures, system Bring-Up & Methodology and, Characterization
 * Demonstrated experience in reading schematics and layout design files to characterize high-speed IOs Interfaces.
 * Knowledge of modern Server uArch (Power, Z, x86, ARM)

## Description

As a Hardware Developer at IBM, you'll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today's market.

Your Role and Responsibilities

As a Memory Software Engineer expected to develop Software and firmware for the following

 * Server memory subsystem initialization and operation
 * Enabling memory characterization activities
 * Validating memory initialization procedure
 * Automating characterization and post silicon validation work flow