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# Digital Verification Engineer

- **Company:** Ai, Inc
- **Location:** Austin, United States
- **Experience:** Experienced
- **Salary:** $130,000.0 - $180,000.0
- **Contract:** Permanent contract
- **Skills:** Automation of Tests, C++ (Programming Language), Computer Engineering, Software Debugging, Data Flow Control, Formal Verification, Python (Programming Language), Log Analysis, Subsystems, System on a Chip, SystemVerilog, Application Specific Integrated Circuits, Agentic-AI
- **Published:** October 26, 2026
- **Apply:** https://startup.jobs/digital-verification-engineer-efficient-computer-10551135

## About the Role

* Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
 * Experience: 4+ years of experience in ASIC/SoC design verification, with multiple projects taken through tapeout.
 * UVM and SystemVerilog: Hands-on experience building and extending UVM testbench components (agents, scoreboards, sequences) and constrained-random tests.
 * Coverage: Experience defining functional coverage and driving code and functional coverage closure at block or subsystem level.
 * Assertions: Working knowledge of SystemVerilog Assertions.
 * Debug Skills: Ability to independently debug simulation failures using waveforms, logs, and design knowledge.
 * Scripting & Automation: Proficiency in Python for test automation, log analysis, and regression flows.
 * Communication: Ability to clearly report verification status and issues to the team.

Ways to Stand Out

 * C/C++ experience for reference models or DPI-based verification.
 * Exposure to formal verification (JasperGold or similar).
 * Experience building or using AI agentic flows for DV.
 * Knowledge of computer architecture or dataflow architectures.
 * Exposure to power-aware verification (UPF)

## Description

* Develop and maintain UVM/SystemVerilog testbenches, sequences, and tests for block- and subsystem-level verification.
 * Write verification plans from design specifications in collaboration with design and architecture teams.
 * Write SystemVerilog assertions and functional coverage models, and drive coverage to closure.
 * Debug simulation failures, working with designers to root-cause and fix issues.
 * Contribute to regression infrastructure, automation, and dashboards that track verification progress.
 * Support gate-level simulation and other sign-off activities.