> Markdown version of [/jobs/ext/3919248-staff-hbm-design-architect-dft](https://www.wearedevelopers.com/jobs/ext/3919248-staff-hbm-design-architect-dft). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# Staff HBM Design Architect - DFT

- **Company:** Micron Technology, Inc.
- **Location:** Richardson, TX, United States
- **Experience:** Expert
- **Salary:** $146,000 - $297,000
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Software Debugging, Dynamic Random-Access Memory, Joint Test Action (IEEE Standards), Application Specific Integrated Circuits, System-level Testing
- **Published:** October 26, 2026
- **Apply:** https://www.techcareers.com/job.asp?id=3466856009&tx=FK5956FFI&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
 * Strong knowledge of scan, MBIST, JTAG, and boundary scan concepts
 * Experience with wafer probe and final test semiconductor flows
 * 5+ years of experience in DRAM or ASIC DFT design or verification, * Experience with HBM, DRAM, or advanced memory products
 * Knowledge of TSV-based 3D integration and stacked-die test challenges
 * Hands-on experience with at-speed test or advanced DFT techniques
 * Exposure to DFT security features or custom customer test interfaces

## Description

As an HBM Design Architect, you will define how next-generation HBM products are tested from wafer to system. This role is critical to ensuring quality, yield, and performance across complex multi-die architectures. You'll influence product success early, work hands-on with silicon, and partner closely with design, test, and manufacturing teams., * Define and implement end-to-end DFT architectures for HBM base die and DRAM die

 * Develop DFT strategies for stacked-die, cube-level, and system-level test flows
 * Architect test access mechanisms supporting wafer probe through final test
 * Enable silicon observability for yield learning, debug, and failure analysis
 * Collaborate across design, verification, layout, test, and manufacturing teams