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# ASIC Digital Design Tech Lead

- **Company:** Cisco Systems, Inc.
- **Location:** Carlsbad, CA, United States
- **Experience:** Expert
- **Salary:** $166,300.0 - $238,300.0
- **Contract:** Permanent contract
- **Skills:** Microarchitecture, Software Debugging, Logic Synthesis of Circuits, Ethernet, Firmware, Field-Programmable Gate Array (FPGA), Subsystems, System on a Chip, Systems Integration, Application Specific Integrated Circuits, Backend
- **Published:** October 26, 2026
- **Apply:** https://www.techcareers.com/job.asp?id=3472095810&tx=UT4844TYZ&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
 * Prior digital design experience working with FSMs, CPU sub-systems, complex SoCs, and FPGA validation,
 * Prior experience in managing the complete ASIC/SoC design flow
 * Prior experience with key bus and interface protocols (e.g., SPI, I2C, APB, AXI) as well as high-speed SerDes, Ethernet, and D2D PHY IP., * End-to-End Silicon Lifecycle & Architecture: Prior experience leading the architecture and design of complex digital blocks and CPU subsystems from pre-silicon RTL to GDS2 signoff, through post-silicon FPGA prototyping, lab validation, and ATE bring-up.
 * Specification & Microarchitecture Design: Prior experience developing top and block-level specifications for high-speed datapath and low-speed control planes, including power/timing budgeting, feedback/control system stability, and hardware vs. firmware trade-offs.
 * Verification, Simulation & IP Integration: Prior experience reviewing verification coverage metrics, independently debugging verification issues, supporting firmware-based verification/architecture, and integrating SerDes and DSP IP.
 * Implementation, Backend & Automation: Hands-on experience with backend implementation activities-including synthesis, timing closure, DFT, low-power design, design automation scripting, and QOR metric processing.
 * Cross-Functional Leadership: Prior experience collaborating across cross-functional engineering teams to resolve technical trade-offs and complex design issues.

## Description

In this high-stakes role, you will define digital architectures, spearhead the integration of cutting-edge high-speed IPs (ODSP, D2D IP, SerDes XSR/PAM4), and optimize power and performance for 100G, 200G, and 400G silicon photonics and Co-Packaged Optics. This is your opportunity to drive technical strategy, pioneer breakthrough interconnect innovations, and deliver silicon that powers the future of high-performance computing.

 * End-to-End Silicon & Subsystem Design: Lead individual design contributions from pre-silicon RTL through GDS2 signoff and post-silicon bring-up (FPGA prototyping, lab validation, and ATE) for complex digital blocks and CPU subsystems.
 * Architecture & Specification: Translate top-level requirements into high-speed datapath and low-speed control plane block specifications-balancing power, timing, loop dynamics, and hardware/firmware trade-offs.
 * Verification & IP Integration: Independently simulate and debug complex design issues, sign off on verification coverage, and support the integration of SerDes and DSP IPs.
 * Backend Implementation & Automation: Support synthesis, DFT, low-power design, and timing closure while developing automation scripts to process Quality of Results (QoR) metrics.
 * Cross-Functional Collaboration: Partner seamlessly with cross-functional teams to resolve technical design challenges and maintain system stability.