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# ASIC Design Verification Technical Leader

- **Company:** Cisco Systems, Inc.
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $186,900.0 - $267,700.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Data Centers, Software Debugging, Perl (Programming Language), Emulators, Ethernet, Formal Verification, Field-Programmable Gate Array (FPGA), Python (Programming Language), PCI Express, SystemVerilog, Scripting, Application Specific Integrated Circuits
- **Published:** October 26, 2026
- **Apply:** https://www.sanjosejobsite.com/job.asp?id=3467044548&tx=VT7065TTD&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Bachelor's degree with 10+ years of related experience, or Master's degree with 7+ years of related experience, or Ph.D. with 5+ years of related experience.
 * Strong experience with SystemVerilog, UVM, and modern verification methodologies, including hardware emulation.
 * Experience developing and executing verification strategies for complex ASIC or SoC programs.
 * Experience leading verification teams or serving as the technical lead for complex verification projects.
 * Proficiency in scripting languages such as Python or Perl, * Experience with Datacenter, Hyperscaler, AI, or networking ASICs.
 * Deep understanding of high-speed protocols (e.g., PCIe, Ethernet, CXL, HBM, DDR) and large-scale SoC architectures.
 * Hands-on experience with hardware emulation platforms such as FPGA prototyping, Cadence Palladium, Siemens Veloce/StratoCS, or Synopsys ZeBu.
 * Experience with silicon bring-up, post-silicon validation, and debug.
 * Experience optimizing verification productivity, regression infrastructure, and automation.
 * Strong technical leadership, communication, collaboration, and mentoring skills

## Description

* Lead the planning and execution of ASIC verification for complex networking SoCs, ensuring high-quality and predictable project execution.
 * Drive verification strategy, testplan development, coverage closure, and execution across multiple IPs and subsystem-level verification efforts.
 * Provide technical leadership and mentorship to verification engineers, promoting best practices and technical excellence.
 * Develop and enhance scalable, reusable verification environments, infrastructure, and methodologies using SystemVerilog/UVM.
 * Collaborate closely with architecture, RTL, emulation, FPGA, and post-silicon teams to enable efficient debug and successful silicon bring-up.
 * Lead complex debug efforts, perform root cause analysis, and drive issues to closure across simulation, emulation, and silicon.
 * Champion continuous improvements in verification productivity, automation, regression efficiency, and quality metrics.
 * Evaluate and adopt new verification technologies, methodologies, and industry best practices to improve verification effectiveness.