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# Lead, DFT and Test Engineer

- **Company:** Celestica, Inc.
- **Location:** Richardson, TX, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Adobe InDesign, Software Debugging, Firmware
- **Published:** October 26, 2026
- **Apply:** https://www.techcareers.com/job.asp?id=3467359741&tx=KP4545FFL&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Strong technical expertise in Design for Testability (DFT) concepts, checking test point access, boundary scan chains, debug access, and provisioning access.
 * Proven hands-on proficiency with Boundary Scan, In-Circuit Testing (ICT), and coverage analysis tooling.
 * Solid capability in modeling structural and functional test coverage against coverage standards (e.g., MTRS).
 * Excellent collaborative problem-solving skills to disposition hardware and software findings across multi-disciplinary teams.
 * Strong cross-functional communication skills to work effectively with schematic, layout, software, firmware, and test engineering stakeholders.

Physical Demands

 * Duties of this position are performed in a normal office environment.
 * Duties may require extended periods of sitting and sustained visual concentration on a computer monitor or on numbers and other detailed data.
 * Repetitive manual movements (e.g., data entry, using a computer mouse, using a calculator, etc.) are frequently required.
 * Occasional travel may be required.

Typical Experience

 * 4 to 8 years of experience in Design for Testability (DFT) or Test Engineering in a complex electronics environment.

Typical Education

 * Bachelor's degree in Electrical Engineering, Electronic Engineering, or a related technical discipline.

## Description

The DFT and Test Engineer runs the testability review inside the design phase. This role is responsible for checking test point access, boundary scan chains, debug access, and provisioning access against established DFT rules, while modeling coverage against the MTRS before layout freeze. Operating at the intersection of Hardware, Software, Firmware, and Test Operations, this position acts as the crucial gatekeeper for testability as an inherent design property and supports functional test definition and early build debug for the assigned site., * Design Reviews: Review schematic and layout against the DFT rule set before freeze, raising findings alongside supporting evidence behind the rule.

 * Coverage Modeling & Verification: Model structural and functional coverage to report gaps against the MTRS, and verify achieved coverage on the first fixture while recording differences against initial claims.
 * Issue Disposition: Collaborate cross-functionally with schematic/layout engineers, software/firmware teams, the program TRL, site test engineering, and the DFT manager to resolve coverage gaps via test point additions, chain corrections, or agreed alternatives.
 * Build & Debug Support: Support functional test definition and early build debug in tandem with the Test Readiness Lead (TRL) and on-site test SMEs.
 * Continuous Improvement: Propose DFT rule changes derived from test escapes and fixture rework feedback to drive ongoing design standards.
 * Ownership & Performance: Own key deliverables-including testability reviews, coverage models against MTRS, DFT findings with formal dispositions, achieved coverage evidence documentation, and rule change proposals. Performance is measured on first-fixture designed-in coverage, pre-freeze closed findings, test escape rates, and repeat findings.