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# Senior Serdes System Design Engineer/Architect

- **Company:** Broadcom
- **Location:** Irvine, CA, United States
- **Experience:** Expert
- **Salary:** $121,900.0 - $195,000.0
- **Contract:** Permanent contract
- **Skills:** Analog Electronics, Systems Engineering, C++ (Programming Language), Computer Programming, Data Recovery, Software Debugging, Firmware, MATLAB, PCI Express, Signal Processing, IEEE 802.3, Application Specific Integrated Circuits
- **Published:** October 26, 2026
- **Apply:** https://www.techcareers.com/job.asp?id=3467770354&tx=HT8074THV&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* B.S.E.E. plus 8+ years relevant experience OR M.S.E.E. plus 6 years required
 * Expert knowledge in Communication Theory
 * Expert knowledge in Digital Signal Processing algorithms
 * Working knowledge of Analog circuit behavior
 * Working knowledge of Transmission line theory and s-parameter
 * Expert in MATLAB, C/C++ programming
 * Good hands-on skills in the lab
 * Experience in designing high-speed Clock and Data Recovery (CDR) PLLs is a very big plus.
 * Experience in equalization techniques for wireline communication applications such as read-channel is also a very big plus.
 * RTL coding is a plus
 * Knowledge of IEEE 802.3/OIF 100G/200G/400G Serdes standards and PCIe Gen6/Gen7 standards is a plus

## Description

This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC designers involved in the design, verification, and implementation of advanced signal processing algorithms for the physical layer of high-speed Serdes at speeds of 100G+.

The types of algorithms that will be implemented include PAM & other higher-order modulation, single/multi-input adaptive equalizers/cancellers, single/multi-dimensioned FEC, digital filters, and interface/integration with analog functions and analysis and compensation for analog circuit non-idealities.

You will be collaborating closely with analog & digital designers to successfully implement the algorithms in advanced silicon technology nodes and work with DVT/lab engineers to validate your designs for high-volume production.

You will support the group contribute to the development of next-generation wireline communications standards at standard bodies such as IEEE and OIF., * Develop channel models and run simulations to help define Serdes architecture

 * Define and document signal processing block requirements, architecture, and lab test plan
 * Develop bit-exact MATLAB and C/C++ system models for simulation and verification
 * Develop and run system-level simulation suites of the Serdes to evaluate architectural tradeoffs
 * Work with the design team to perform vector matching verification with RTL simulations
 * Develop, test, and debug firmware associated with physical layer functionality
 * Lab testing and debug of Serdes
 * Documentation/application note development and customer support
 * Support marketing group with customer meetings and collateral