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# Mixed Signal Digital Design Lead

- **Company:** Broadcom
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $121,900.0 - $195,000.0
- **Contract:** Permanent contract
- **Skills:** Analog Electronics, Boolean Algebra, Logic Synthesis of Circuits, SystemVerilog, Systems Integration, Application Specific Integrated Circuits, State Machines, Physical Design
- **Published:** October 26, 2026
- **Apply:** https://www.sanjosejobsite.com/job.asp?id=3467770195&tx=JJ8175FFJ&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Education: Bachelors degree
 * Experience: 8+ years of professional digital ASIC design experience.
 * RTL Mastery: Deep expertise in writing robust, synthesizable SystemVerilog RTL
 * Process Nodes: Direct experience with advanced technology nodes, specifically N5, N3P, and beyond .
 * Track Record: Proven history of steering cross-functional execution from initial concept through to successful tapeouts.

## Description

We are seeking a Digital Mixed-Signal Lead with a strong digital design and architecture background to lead the development of digital control infrastructures for advanced clocking sub-systems ( PLLs, FLLs, and DLLs ).

Core Responsibilities

 * Architecture & RTL: Own the architectural definition, RTL implementation, and system-level integration of the digital logic driving clocking IPs.
 * Logic Design: Design complex digital control loops, state machines for adaptive calibration, DVFS (dynamic voltage/frequency scaling) controllers, and fractional-N delta-sigma modulators.
 * Analog Interface: Serve as the primary bridge to Analog Circuit Designers. Translate analog specifications into robust digital architectures and define clean boundaries at the analog-digital interface.
 * Verification Partnership: Partner with Verification Teams to drive Mixed-Signal Verification (MSV) and Real Number Modeling (RNM) strategies for high-coverage loop simulations.
 * Physical Design Collaboration: Work with Physical Design Teams to co-optimize floorplanning and protect sensitive analog nodes from digital switching noise.
 * Sign-off Methodology: Enforce a rigorous full-chip CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) sign-off methodology for the clocking network.