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# High-Speed SerDes Design Engineer - Acacia (Hybrid)

- **Company:** Cisco Systems, Inc.
- **Location:** San Jose, CA, United States
- **Salary:** $171,600.0 - $245,000.0
- **Contract:** Permanent contract
- **Skills:** Adobe InDesign, Hardware Design, MATLAB, Cadence Virtuoso, Application Specific Integrated Circuits
- **Published:** October 26, 2026
- **Apply:** https://www.sanjosejobsite.com/job.asp?id=3467044333&tx=FL636FFI&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

You are enthusiastic about developing high speed AMS circuits and best-in-class products that push the boundaries of what is possible. You are detail oriented, high energy and the drive to get things done and solve difficult problems.

You are capable to figure things out by yourself, but you also participate in our friendly and team-oriented collaboration approach, which means you enjoy learning from your colleagues and letting them learn from you.

You are not shy to always point out how we can be more effective as a team, and you are open to similar suggestions by your team members.

Minimum qualification

Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience.

Experience in design, simulation and measurement of high speed ICs in at least 3 of the areas listed below:

 * High Speed Serial Links utilizing serializers, deserializers, and data convertors.
 * Modeling requirements for system link simulations
 * High Performance Output Drivers
 * High Performance Phase Locked Loops
 * Efficient clock transmission/propagation.
 * Opamps and Programmable Gain Amplifiers.
 * Equalization techniques.

Preferred Qualifications

Experience with electrical transceiver applications including backplane and cable communications.

 * Experience in FinFET and GAA technologies.
 * High-frequency layout experience including floorplaning (power/ground, digital/analog signal routing), passives components (inductors, transformers, and transmission-lins).
 * Experience in design for manufacturability including characterization over PVT, electromigration analysis,self-heating, and IR drop analysis.
 * Experience in laboratory validation including ESD practices/methodology and construction of test setups.
 * Experience in design software including Cadence (Virtuoso), Specture/APS/SpectreX, layout validation tools (Virtuoso and Calibre), EMX, mixed-signal simulations in AMS, and Matlab.

## Description

You will work with other Acacia mixed-signal engineers to collaborate in order to provide an optimized design that will integrate into the ASIC. In addition, you will have the opportunity to interact with other Acacia groups including digital/DSP design, system design, package design, and module design. Acacia takes pride in providing and fostering a collaborate environment in order ensure success and personal growth.

Your Impact

As a member of the Mixed Signal Design team, you will be a key member of a small, dynamic IC Design group that develops high speed ()25Gb/s), and high accuracy, analog designs for optical communications products. You will architect, design, layout, measure and productize ultra-deep sub-micron-based CMOS products.

You will lead efforts for a large block on a complex chip, mentor team members and track deliverables, participate in peer review of complex IC designs and provide solid design methodology from conception to production.

You will also collaborate with packaging and hardware design team to ensure signal and power integrity specifications are met.