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# Senior ASIC Engineer

- **Company:** Cisco Systems, Inc.
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $167,700.0 - $245,200.0
- **Contract:** Permanent contract
- **Skills:** C++ (Programming Language), Code Review, Software Debugging, Linux, Perl (Programming Language), Python (Programming Language), Subsystems, SystemVerilog, Application Specific Integrated Circuits, Physical Design
- **Published:** October 26, 2026
- **Apply:** https://www.sanjosejobsite.com/job.asp?id=3467044751&tx=FP6158FFI&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54

## About the Role

* Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 2 years of related experience
 * Experience with ASIC design and verification processes (with System Verilog), debugging, methodology, and tools., * Experience with dashboard management for regression, coverage, test list completion and other DV statistics.
 * Post-silicon lab bring-up experience.
 * Experience in leading the verification methodology (in UVM) of clusters/subsystems or full chip level for ASIC.
 * Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS
 * Experience with Linux, C/C++, and/or Python/Perl.
 * Experience in Networking.

## Description

* Drives the definition, architecture and design and verification of high performance ASICs
 * Owns complex or multiple functional areas
 * Develops reusable code for future projects
 * Creates re-usable code
 * Debugs at ASIC, SW, HW level
 * Works with ASIC and Apps, with limited external scope
 * Leads design and DV work by solving block level issues and participates in chip level issue resolution
 * Drives reviews and recognizes areas of architectural concerns
 * Defines new verification methodologies
 * Helps in lab bring up
 * Leads code reviews at platform level