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# Quantum Design Enablement Engineer

- **Company:** Ionq, Inc.
- **Location:** Berwyn Heights, MD, United States
- **Experience:** Experienced
- **Salary:** $126,887.0 - $166,127.0
- **Contract:** Permanent contract
- **Skills:** Amazon Web Services, Computer Networks, Internet Security, Python (Programming Language), Micro Electro-Mechanical Systems (MEMS), Quantum Computing, Cadence Virtuoso, Linux Virtual Server, Git, Physical Verification
- **Published:** October 27, 2026
- **Apply:** https://www.careerbuilder.com/job-details/quantum-design-enablement-engineer-berwyn-heights-md--bac6df84-7404-4cbe-8fad-009ea45b53d6

## About the Role

Technical/Engineering Design, Internet Security, Logistics, Drug Discovery, Quantum Computing, Financial Modeling, Material Science, Customer Support/Service, Amazon Web Services (AWS), Computer Networks, * Bachelor's or Master's degree in Electrical Engineering, Physics, Materials Science, or a related technical field.

 * 3 - 5 years of industry experience in semiconductor manufacturing, design enablement, tapeout operations, or a closely related field.
 * Hands-on experience with physical verification tools (such as Siemens Calibre, Cadence Pegasus, or Synopsys IC Validator) and running standard DRC, LVS, and ERC checks.
 * Proficiency with standard layout and viewing tools like Cadence Virtuoso or KLayout, including the ability to perform layout edits and detailed mask reviews.
 * Strong understanding of PDK architecture and technology files, as well as how foundry design rules dictate layout methodologies.
 * Exceptional cross-functional communication skills, with demonstrated ability to negotiate technical requirements between external fab engineers and internal design teams., * Strong proficiency in Python and hands-on experience with Python-based layout generation frameworks (such as gdsfactory, gdspy or the KLayout), alongside version control using Git.
 * Experience with non-traditional semiconductor and microfabrication technologies, such as integrated photonics, MEMS, or specialized BEOL metallization.
 * Experience writing or modifying custom physical verification rules (such as Calibre SVRF/TVF or equivalent) to develop layout rules specific to trapped-ion quantum computing hardware.
 * Familiarity with standard CMOS device modeling principles and compact modeling methodologies.
 * Understanding of Parasitic Extraction (PEX) flows and tools, with an awareness of how physical layout impacts parasitic capacitances, RF performance, and device behavior.

## Description

* Foundry Interface & PDK Management: Serve as the primary technical point of contact with external foundry partners. Work collaboratively to define, implement, and troubleshoot the PDK, ensuring it accurately reflects foundry capabilities and constraints.
 * Tapeout & Mask Validation: Own the tapeout process. Perform comprehensive mask layout validation, execute physical verification (DRC/LVS), and ensure final GDSII/OASIS files are fully compliant with foundry requirements before handoff.
 * Design Team Enablement: Act as a liaison between manufacturing and core product design teams. Translate complex foundry requirements and process updates into clear design rules and best practices for design engineers.
 * Layout & Integration: Perform hands-on layout modifications, frame generation, and reticle assembly as needed to finalize masks for manufacturing. Generate custom layouts for test structures, process monitos, or simple test chips when necessary.
 * Rule Deck Customization: Work primarily with foundry-provided DRC/LVS rule decks while taking the initiative to write, modify, and optimize custom internal rule checks for specialized trapped-ion quantum computer design constraints.
 * Continuous Improvement: Analyze tapeout data and foundry feedback to proactively drive improvements in the PDK, design rules, and overall design-to-manufacturing workflow.