> Markdown version of [/jobs/ext/3954610-senior-digital-verification-engineer](https://www.wearedevelopers.com/jobs/ext/3954610-senior-digital-verification-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior Digital Verification Engineer - **Company:** EfficientAI Corporation - **Location:** Austin, TX, United States - **Experience:** Expert - **Salary:** $160,000.0 - $245,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Application Frameworks, Automation of Tests, C++ (Programming Language), Code Coverage, Computer Engineering, Data Centers, Software Debugging, Firmware, Formal Verification, Python (Programming Language), Log Analysis, Reduced Instruction Set Computing, Software Engineering, System on a Chip, SystemVerilog, Computer Network Operations, Application Specific Integrated Circuits, Agentic-AI, Wearables, Programming Languages - **Published:** October 27, 2026 - **Apply:** https://www.careerbuilder.com/job-details/senior-digital-verification-engineer-austin-tx--1b3a00a3-3d98-4659-b7f0-d524f4b1a03c ## About the Role Verification Engineering, Programming Languages, Energy Efficiency, Network Operations Center, Wearables, Artificial Intelligence (AI), Software Engineering, Functional Testing, Verification Engineering, Design Verification, * Education: Bachelor''s or Master''s/PhD degree in Electrical Engineering, Computer Engineering, or a related field. * Experience: 10+ years of progressive experience in ASIC/SoC design verification with multiple full cycles of ownership from testbench architecture through tapeout. * UVM and SystemVerilog: Expertise in UVM-based testbench architecture and constrained-random verification methodology * C/C++ experience for modelling or verification. * Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs. * Debug Skills: Proven ability to debug complex simulation failures. * Scripting & Automation: Proficiency in Python for test automation, log analysis, coverage post-processing, and regression flow development. * Communication: Ability to clearly communicate verification risk, status and tradeoffs to technical peers and program leadership. Ways to stand out : * Experience in Formal verification (JasperGold or similar). * Experience building or using AI Agentic flows for DV. * Software/Firmware based testing experience and working with software teams pre-silicon * Post-silicon experience * SoC Architecture: Understanding and experience in some of the following areas : processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals. * Power aware verification and UPF ## Description Efficient Computer is rethinking computing from the ground up to solve one of AI''s biggest challenges: energy. Our Fabric architecture delivers a 10-100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks-unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we''re accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it''s needed and help shape the next generation of computing.