> Markdown version of [/jobs/ext/3963362-senior-fpga-engineer-dod-cleared](https://www.wearedevelopers.com/jobs/ext/3963362-senior-fpga-engineer-dod-cleared). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior FPGA Engineer (DOD cleared) - **Company:** Associates, Inc - **Location:** Tucson, AZ, United States - **Experience:** Expert - **Contract:** Contract - **Skills:** Systems Engineering, Software Debugging, Logic Synthesis of Circuits, Field-Programmable Gate Array (FPGA), Hardware Description Language, Software Requirements Analysis, SystemVerilog, VHSIC Hardware Description Language (VHDL), SC Clearance, Physical Design - **Published:** October 27, 2026 - **Apply:** https://www.careerbuilder.com/job-details/senior-fpga-engineer-dod-cleared-tucson-az--1ba27c5e-0a80-4f57-8586-99d7ea16ac22 ## About the Role FPGA, United States Department of Defense (DoD), Negotiation Skills, FPGA, Secret Clearance, Debugging Skills, Production Support, Place and Route, VHDL Hardware Description Language, FPGA Design, * 8+ years of FPGA engineering experience. * VHDL coding and digital design experience. * Experience with Xilinx, Altera, or Microsemi FPGA devices and tool flows. * Hands-on FPGA integration and debug experience. * Experience delivering FPGA solutions into system-level applications. * Ability to support FPGA work from requirements definition through integration and test. * Secret clearance or higher required prior to start. Preferred Skills * Radar or image processing experience. * Embedded systems experience using ARM, MicroBlaze, or Nios processors. * Experience with gigabit serial interfaces or multi-gigabit transceivers. * SystemVerilog / UVM verification experience. * Experience with emulation platforms such as Veloce. * Strong technical documentation and review support experience. #cj ## Description All Qualified candidates will be responded to in 24 hours or less Interim Secret required prior to start Employment type: Full Time W-2 or Contract Rate: open to Negotiation Benefits: including Health, Dental Vision, PTO, Holidays, 401K,etc, * Develop and verify FPGA designs using VHDL. * Support FPGA architectures for system-level applications. * Translate system-level requirements into FPGA requirements. * Perform simulation, synthesis, place-and-route, timing closure, integration, and debug. * Work with circuit card designers and systems engineers to define interfaces and design requirements. * Support FPGA designs involving RF/EO DSP, controls, data links, embedded processing, processor interfaces, and gigabit serial interfaces. * Create technical documentation, including requirements, verification plans, and user guides. * Support internal and external technical reviews as needed.