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# Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs

- **Company:** Amazon.com, Inc.
- **Location:** Cupertino, CA, United States
- **Experience:** Expert
- **Salary:** $213,000 - $287,500
- **Contract:** Permanent contract
- **Skills:** Very-Large-Scale Integration, Software Quality, Computer Engineering, Microarchitecture, Software Debugging, Python (Programming Language), Machine Learning, SystemVerilog, Scripting, Application Specific Integrated Circuits
- **Published:** October 27, 2026
- **Apply:** https://www.jobmonkeyjobs.com/career/28133164/Sr-Asic-Design-Engineer-Cloud-Scale-Machine-Learning-Acceleration-Team-Annapurna-Labs-California-Cupertino-7375

## About the Role

Are familiar with scripting in Python

 - Are proficient with assertions
 - Have good debug skills to analyze RTL test failures
 - Have a "Learn and Be Curious" mindset, Bachelor's degree in Electrical Engineering or a related field
 - 5+ years in RTL design for SOC
 - 5+ years in VLSI engineering
 - 5+ years with code quality tools including: Spyglass, LINT, or CDC

Preferred Qualifications

 - Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs
 - Master's degree in electrical engineering, computer engineering, or equivalent
 - 5+ years of practical semiconductor design work including full-chip and subsystem integration experience
 - Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints
 - Experience with automation and scripting languages such as Python
 - Familiarity with data path design, interconnects, AXI protocol
 - Good analytical, problem solving, and communication skills

## Description

As a key member of the ASIC design team, you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications.

 - Integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/DFT signal routing
 - Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements.
 - Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints.
 - Perform lint and clock domain crossing quality checks on the design.
 - Work with with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing and back-end teams to accomplish your tasks.