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# Software Engineer - AI for RTL Design & Formal Verification

- **Company:** Astera Labs
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $160,500.0 - $200,000.0
- **Contract:** Permanent contract
- **Skills:** Computer-Aided Design, Artificial Intelligence, Continuous Integration, Data Structures, Formal Verification, Hardware Design, Machine Learning, Performance Tuning, Rapid Prototyping Process, Software Engineering, Static Timing Analysis, SystemVerilog, Verilog, Software Verification, Retrieval-Augmented Generation, Large Language Models, Multi-Agent Systems, Information Technology, Software Version Control
- **Published:** October 27, 2026
- **Apply:** https://startup.jobs/formal-verification-and-rtl-design-software-engineer-astera-labs-9818732

## About the Role

* Bachelor's, Master's degree in Electrical Engineering, Computer Science/Engineering, or equivalent experience.
 * 4-10 years of industry experience in software engineering, with direct exposure to RTL design, static/lint verification, or formal verification methodologies.
 * Proficiency in Python for rapid prototyping, with strong fundamentals in data structures, algorithms, and software engineering practices.
 * Experience with LLMs, including fine-tuning, building multi-agent systems, RAG pipelines, and vector databases.
 * Familiarity with RTL design languages (Verilog/SystemVerilog) and formal/static verification tools (e.g., JasperGold, VC Formal, or similar) is strongly preferred.
 * Strong analytical, communication, and interpersonal skills, with a proven ability to work effectively in a fast-paced, cross-functional startup environment.
 * A proactive, self-directed approach to problem-solving and comfort operating with ambiguity.

Ways to Stand Out

 * Direct experience applying AI/ML techniques to EDA or CAD flow problems.
 * Proficiency in modern software engineering practices, including version control, testing, and CI/CD.
 * Experience with formal property verification, assertion-based verification (SVA), or static timing/lint tools.
 * A track record of learning across disparate domains (AI/ML and hardware design) and combining them into novel engineering solutions.